70 lines
582 B
Plaintext
70 lines
582 B
Plaintext
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$date
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Sat Feb 28 20:25:22 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module full_adder_tb $end
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$var wire 1 ! carry_out $end
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$var wire 1 " sum $end
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$var reg 1 # a $end
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$var reg 1 $ b $end
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$var reg 1 % carry_in $end
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$scope module full_adder $end
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$var wire 1 & a $end
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$var wire 1 ' b $end
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$var wire 1 ( carry_in $end
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$var reg 1 ) carry_out $end
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$var reg 1 * sum $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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0*
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0)
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0(
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0'
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0&
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0%
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0$
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0#
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0"
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0!
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$end
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#1
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1*
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1"
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1%
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1(
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#2
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0*
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0"
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0%
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0(
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#3
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1*
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1"
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1#
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1&
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#4
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1)
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1!
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0*
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0"
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1%
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1(
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#5
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0%
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0(
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1$
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1'
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#6
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1*
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1"
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1%
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1(
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