54 lines
1.3 KiB
Coq
54 lines
1.3 KiB
Coq
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/*
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Ram Sincrona testbench
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*/
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`include "ram/ram.v"
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module ram_tb;
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reg clk, wr_en;
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reg [7:0] addr;
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reg [15:0] wr_data;
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wire [15:0] rd_data;
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ram ram1(
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.clk(clk),
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.wr_en(wr_en),
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.addr(addr),
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.wr_data(wr_data),
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.rd_data(rd_data)
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);
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initial clk = 0;
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always #5 clk = ~clk;
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initial begin
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$dumpfile("ram/ram.vcd");
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$dumpvars(0, ram_tb);
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wr_en = 0; addr = 0; wr_data = 0;
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@(posedge clk);
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$display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
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wr_en = 1; addr = 25; wr_data = 256;
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@(posedge clk);
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$display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
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wr_en = 0;
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@(posedge clk);
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$display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
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@(posedge clk);
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$display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
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addr = 16;
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@(posedge clk);
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$display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
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@(posedge clk);
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$display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
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$finish;
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end
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endmodule
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