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hdl-projects/decoder_encoder/decoder_encoder.v

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2026-03-01 01:02:44 +01:00
/*
Decoder / Encoder
*/
module decoder_3bit (
input [2:0] in,
output [7:0] out
);
assign out = 1 << in;
endmodule
module encoder_3bit(
input [7:0] in,
output reg [2:0] out
);
always @(*) begin
out = 0;
casez(in)
8'b1???????: out = 3'd7;
8'b01??????: out = 3'd6;
8'b001?????: out = 3'd5;
8'b0001????: out = 3'd4;
8'b00001???: out = 3'd3;
8'b000001??: out = 3'd2;
8'b0000001?: out = 3'd1;
8'b00000001: out = 3'd0;
endcase
end
endmodule