17 lines
282 B
Coq
17 lines
282 B
Coq
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/*
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Flip-Flop D y registro
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*/
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module register #(parameter N = 8)(
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input clk,
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input rst,
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input en,
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input [N-1:0] d,
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output reg [N-1:0] q
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);
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always @(posedge clk or posedge rst) begin
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if (rst) q <= 0;
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else if (en) q <= d;
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end
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endmodule
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