hdl-projects/adder_nbit/adder_nbit.vvp

#! /c/iverilog/bin/vvp
:ivl_version "0.9.7 " "(v0_9_7)";
:vpi_time_precision + 0;
:vpi_module "system";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0118C068 .scope module, "adder_nbit_tb" "adder_nbit_tb" 2 3;
 .timescale 0 0;
v011CE8B0_0 .var "a", 7 0;
v011CE3E0_0 .var "b", 7 0;
v011CE750_0 .var "carry_in", 0 0;
v011CE800_0 .net "carry_out", 0 0, L_011D03D8; 1 drivers
RS_0119B434/0/0 .resolv tri, L_011CEDD8, L_011CED80, L_011D0010, L_011CF880;
RS_0119B434/0/4 .resolv tri, L_011CF720, L_011CFFB8, L_011CFAE8, L_011D00C0;
RS_0119B434 .resolv tri, RS_0119B434/0/0, RS_0119B434/0/4, C4<zzzzzzzz>, C4<zzzzzzzz>;
v011CE7A8_0 .net8 "sum", 7 0, RS_0119B434; 8 drivers
S_0118BE48 .scope module, "adder_8bit" "adder_nbit" 2 10, 3 6, S_0118C068;
 .timescale 0 0;
P_01190EEC .param/l "N" 3 6, +C4<01000>;
L_011D0B48 .functor BUFZ 1, v011CE750_0, C4<0>, C4<0>, C4<0>;
v011CE540_0 .net *"_s59", 0 0, L_011D0B48; 1 drivers
v011CE6F8_0 .net "a", 7 0, v011CE8B0_0; 1 drivers
v011CE438_0 .net "b", 7 0, v011CE3E0_0; 1 drivers
RS_0119B3EC/0/0 .resolv tri, L_011CEAC0, L_011CFCA0, L_011CF930, L_011CF8D8;
RS_0119B3EC/0/4 .resolv tri, L_011CF9E0, L_011CFB98, L_011CFB40, L_011CFEB0;
RS_0119B3EC/0/8 .resolv tri, L_011CF7D0, C4<zzzzzzzzz>, C4<zzzzzzzzz>, C4<zzzzzzzzz>;
RS_0119B3EC .resolv tri, RS_0119B3EC/0/0, RS_0119B3EC/0/4, RS_0119B3EC/0/8, C4<zzzzzzzzz>;
v011CE070_0 .net8 "carry", 8 0, RS_0119B3EC; 9 drivers
v011CE2D8_0 .net "carry_in", 0 0, v011CE750_0; 1 drivers
v011CE858_0 .alias "carry_out", 0 0, v011CE800_0;
v011CE120_0 .alias "sum", 7 0, v011CE7A8_0;
L_011CED28 .part RS_0119B3EC, 0, 1;
L_011CEBC8 .part v011CE8B0_0, 0, 1;
L_011CEB70 .part v011CE3E0_0, 0, 1;
L_011CEDD8 .part/pv L_011CDAF8, 0, 1, 8;
L_011CEAC0 .part/pv L_011CDA88, 1, 1, 9;
L_011CEC20 .part RS_0119B3EC, 1, 1;
L_011CE960 .part v011CE8B0_0, 1, 1;
L_011CEC78 .part v011CE3E0_0, 1, 1;
L_011CED80 .part/pv L_011CF060, 1, 1, 8;
L_011CFCA0 .part/pv L_011CEED8, 2, 1, 9;
L_011CF828 .part RS_0119B3EC, 2, 1;
L_011CFCF8 .part v011CE8B0_0, 2, 1;
L_011CFF08 .part v011CE3E0_0, 2, 1;
L_011D0010 .part/pv L_011CF140, 2, 1, 8;
L_011CF930 .part/pv L_011CEEA0, 3, 1, 9;
L_011CF988 .part RS_0119B3EC, 3, 1;
L_011CFDA8 .part v011CE8B0_0, 3, 1;
L_011D0068 .part v011CE3E0_0, 3, 1;
L_011CF880 .part/pv L_011CEE68, 3, 1, 8;
L_011CF8D8 .part/pv L_011CF0D0, 4, 1, 9;
L_011CFD50 .part RS_0119B3EC, 4, 1;
L_011CFC48 .part v011CE8B0_0, 4, 1;
L_011CF670 .part v011CE3E0_0, 4, 1;
L_011CF720 .part/pv L_011CEFF0, 4, 1, 8;
L_011CF9E0 .part/pv L_011CDC80, 5, 1, 9;
L_011CFA38 .part RS_0119B3EC, 5, 1;
L_011CF778 .part v011CE8B0_0, 5, 1;
L_011CFA90 .part v011CE3E0_0, 5, 1;
L_011CFFB8 .part/pv L_011CEF80, 5, 1, 8;
L_011CFB98 .part/pv L_011D0918, 6, 1, 9;
L_011CFF60 .part RS_0119B3EC, 6, 1;
L_011CFE00 .part v011CE8B0_0, 6, 1;
L_011CF6C8 .part v011CE3E0_0, 6, 1;
L_011CFAE8 .part/pv L_011D0AD8, 6, 1, 8;
L_011CFB40 .part/pv L_011D0B80, 7, 1, 9;
L_011CFBF0 .part RS_0119B3EC, 7, 1;
L_011D0118 .part v011CE8B0_0, 7, 1;
L_011CFE58 .part v011CE3E0_0, 7, 1;
L_011D00C0 .part/pv L_011D07C8, 7, 1, 8;
L_011CFEB0 .part/pv L_011D0870, 8, 1, 9;
L_011CF7D0 .part/pv L_011D0B48, 0, 1, 9;
L_011D03D8 .part RS_0119B3EC, 8, 1;
S_0118A908 .scope generate, "generar_full_adder[0]" "generar_full_adder[0]" 3 19, 3 19, S_0118BE48;
 .timescale 0 0;
P_011910EC .param/l "i" 3 19, +C4<00>;
S_0118AF68 .scope module, "full_adder" "full_adder_structural" 3 20, 4 16, S_0118A908;
 .timescale 0 0;
L_011CDA88 .functor OR 1, L_011CDC48, L_011CDBD8, C4<0>, C4<0>;
v011CD708_0 .net "a", 0 0, L_011CEBC8; 1 drivers
v011CD7B8_0 .net "add1_carry", 0 0, L_011CDC48; 1 drivers
v011CD760_0 .net "add1_sum", 0 0, L_011CDD98; 1 drivers
v011CD868_0 .net "add2_carry", 0 0, L_011CDBD8; 1 drivers
v011CD8C0_0 .net "b", 0 0, L_011CEB70; 1 drivers
v011CE0C8_0 .net "carry_in", 0 0, L_011CED28; 1 drivers
v011CE018_0 .net "carry_out", 0 0, L_011CDA88; 1 drivers
v011CDEB8_0 .net "sum", 0 0, L_011CDAF8; 1 drivers
S_0118AB28 .scope module, "add1" "half_adder" 4 23, 5 5, S_0118AF68;
 .timescale 0 0;
L_011CDD98 .functor XOR 1, L_011CEBC8, L_011CEB70, C4<0>, C4<0>;
L_011CDC48 .functor AND 1, L_011CEBC8, L_011CEB70, C4<1>, C4<1>;
v011CD9C8_0 .alias "a", 0 0, v011CD708_0;
v011CD658_0 .alias "b", 0 0, v011CD8C0_0;
v011CD810_0 .alias "carry", 0 0, v011CD7B8_0;
v011CD6B0_0 .alias "sum", 0 0, v011CD760_0;
S_0118B650 .scope module, "add2" "half_adder" 4 24, 5 5, S_0118AF68;
 .timescale 0 0;
L_011CDAF8 .functor XOR 1, L_011CDD98, L_011CED28, C4<0>, C4<0>;
L_011CDBD8 .functor AND 1, L_011CDD98, L_011CED28, C4<1>, C4<1>;
v011CD550_0 .alias "a", 0 0, v011CD760_0;
v011CD5A8_0 .alias "b", 0 0, v011CE0C8_0;
v011CD918_0 .alias "carry", 0 0, v011CD868_0;
v011CD600_0 .alias "sum", 0 0, v011CDEB8_0;
S_0118B4B8 .scope generate, "generar_full_adder[1]" "generar_full_adder[1]" 3 19, 3 19, S_0118BE48;
 .timescale 0 0;
P_011910CC .param/l "i" 3 19, +C4<01>;
S_0118AEE0 .scope module, "full_adder" "full_adder_structural" 3 20, 4 16, S_0118B4B8;
 .timescale 0 0;
L_011CEED8 .functor OR 1, L_011CF3A8, L_011CF3E0, C4<0>, C4<0>;
v011CD398_0 .net "a", 0 0, L_011CE960; 1 drivers
v011CD3F0_0 .net "add1_carry", 0 0, L_011CF3A8; 1 drivers
v011CD4F8_0 .net "add1_sum", 0 0, L_011CDB68; 1 drivers
v011CCAA8_0 .net "add2_carry", 0 0, L_011CF3E0; 1 drivers
v011CCB00_0 .net "b", 0 0, L_011CEC78; 1 drivers
v011CCB58_0 .net "carry_in", 0 0, L_011CEC20; 1 drivers
v011CCBB0_0 .net "carry_out", 0 0, L_011CEED8; 1 drivers
v011CD970_0 .net "sum", 0 0, L_011CF060; 1 drivers
S_0118B7E8 .scope module, "add1" "half_adder" 4 23, 5 5, S_0118AEE0;
 .timescale 0 0;
L_011CDB68 .functor XOR 1, L_011CE960, L_011CEC78, C4<0>, C4<0>;
L_011CF3A8 .functor AND 1, L_011CE960, L_011CEC78, C4<1>, C4<1>;
v011CCA50_0 .alias "a", 0 0, v011CD398_0;
v011CD238_0 .alias "b", 0 0, v011CCB00_0;
v011CD290_0 .alias "carry", 0 0, v011CD3F0_0;
v011CCE70_0 .alias "sum", 0 0, v011CD4F8_0;
S_0118B320 .scope module, "add2" "half_adder" 4 24, 5 5, S_0118AEE0;
 .timescale 0 0;
L_011CF060 .functor XOR 1, L_011CDB68, L_011CEC20, C4<0>, C4<0>;
L_011CF3E0 .functor AND 1, L_011CDB68, L_011CEC20, C4<1>, C4<1>;
v011CCDC0_0 .alias "a", 0 0, v011CD4F8_0;
v011CCE18_0 .alias "b", 0 0, v011CCB58_0;
v011CCFD0_0 .alias "carry", 0 0, v011CCAA8_0;
v011CD1E0_0 .alias "sum", 0 0, v011CD970_0;
S_0118B298 .scope generate, "generar_full_adder[2]" "generar_full_adder[2]" 3 19, 3 19, S_0118BE48;
 .timescale 0 0;
P_0119130C .param/l "i" 3 19, +C4<010>;
S_0118AA18 .scope module, "full_adder" "full_adder_structural" 3 20, 4 16, S_0118B298;
 .timescale 0 0;
L_011CEEA0 .functor OR 1, L_011CEF48, L_011CF290, C4<0>, C4<0>;
v011CD448_0 .net "a", 0 0, L_011CFCF8; 1 drivers
v011CCCB8_0 .net "add1_carry", 0 0, L_011CEF48; 1 drivers
v011CD4A0_0 .net "add1_sum", 0 0, L_011CF098; 1 drivers
v011CCD10_0 .net "add2_carry", 0 0, L_011CF290; 1 drivers
v011CCF78_0 .net "b", 0 0, L_011CFF08; 1 drivers
v011CD080_0 .net "carry_in", 0 0, L_011CF828; 1 drivers
v011CD188_0 .net "carry_out", 0 0, L_011CEEA0; 1 drivers
v011CCD68_0 .net "sum", 0 0, L_011CF140; 1 drivers
S_0118B980 .scope module, "add1" "half_adder" 4 23, 5 5, S_0118AA18;
 .timescale 0 0;
L_011CF098 .functor XOR 1, L_011CFCF8, L_011CFF08, C4<0>, C4<0>;
L_011CEF48 .functor AND 1, L_011CFCF8, L_011CFF08, C4<1>, C4<1>;
v011CD2E8_0 .alias "a", 0 0, v011CD448_0;
v011CD028_0 .alias "b", 0 0, v011CCF78_0;
v011CCC60_0 .alias "carry", 0 0, v011CCCB8_0;
v011CCEC8_0 .alias "sum", 0 0, v011CD4A0_0;
S_0118B6D8 .scope module, "add2" "half_adder" 4 24, 5 5, S_0118AA18;
 .timescale 0 0;
L_011CF140 .functor XOR 1, L_011CF098, L_011CF828, C4<0>, C4<0>;
L_011CF290 .functor AND 1, L_011CF098, L_011CF828, C4<1>, C4<1>;
v011CD340_0 .alias "a", 0 0, v011CD4A0_0;
v011CD130_0 .alias "b", 0 0, v011CD080_0;
v011CCC08_0 .alias "carry", 0 0, v011CCD10_0;
v011CD0D8_0 .alias "sum", 0 0, v011CCD68_0;
S_0118AE58 .scope generate, "generar_full_adder[3]" "generar_full_adder[3]" 3 19, 3 19, S_0118BE48;
 .timescale 0 0;
P_011913AC .param/l "i" 3 19, +C4<011>;
S_0118B188 .scope module, "full_adder" "full_adder_structural" 3 20, 4 16, S_0118AE58;
 .timescale 0 0;
L_011CF0D0 .functor OR 1, L_011CF450, L_011CEFB8, C4<0>, C4<0>;
v011CC6A8_0 .net "a", 0 0, L_011CFDA8; 1 drivers
v011CC7B0_0 .net "add1_carry", 0 0, L_011CF450; 1 drivers
v011CC700_0 .net "add1_sum", 0 0, L_011CF1E8; 1 drivers
v011CC808_0 .net "add2_carry", 0 0, L_011CEFB8; 1 drivers
v011CC860_0 .net "b", 0 0, L_011D0068; 1 drivers
v011CC8B8_0 .net "carry_in", 0 0, L_011CF988; 1 drivers
v011CC910_0 .net "carry_out", 0 0, L_011CF0D0; 1 drivers
v011CCF20_0 .net "sum", 0 0, L_011CEE68; 1 drivers
S_0118ABB0 .scope module, "add1" "half_adder" 4 23, 5 5, S_0118B188;
 .timescale 0 0;
L_011CF1E8 .functor XOR 1, L_011CFDA8, L_011D0068, C4<0>, C4<0>;
L_011CF450 .functor AND 1, L_011CFDA8, L_011D0068, C4<1>, C4<1>;
v011CC5A0_0 .alias "a", 0 0, v011CC6A8_0;
v011CC5F8_0 .alias "b", 0 0, v011CC860_0;
v011CC650_0 .alias "carry", 0 0, v011CC7B0_0;
v011CC9C0_0 .alias "sum", 0 0, v011CC700_0;
S_0118B210 .scope module, "add2" "half_adder" 4 24, 5 5, S_0118B188;
 .timescale 0 0;
L_011CEE68 .functor XOR 1, L_011CF1E8, L_011CF988, C4<0>, C4<0>;
L_011CEFB8 .functor AND 1, L_011CF1E8, L_011CF988, C4<1>, C4<1>;
v011CC1D8_0 .alias "a", 0 0, v011CC700_0;
v011CC758_0 .alias "b", 0 0, v011CC8B8_0;
v011CC968_0 .alias "carry", 0 0, v011CC808_0;
v011CC548_0 .alias "sum", 0 0, v011CCF20_0;
S_0118BED0 .scope generate, "generar_full_adder[4]" "generar_full_adder[4]" 3 19, 3 19, S_0118BE48;
 .timescale 0 0;
P_011912EC .param/l "i" 3 19, +C4<0100>;
S_0118BF58 .scope module, "full_adder" "full_adder_structural" 3 20, 4 16, S_0118BED0;
 .timescale 0 0;
L_011CDC80 .functor OR 1, L_011CF338, L_011CF5D8, C4<0>, C4<0>;
v011CC440_0 .net "a", 0 0, L_011CFC48; 1 drivers
v011CC128_0 .net "add1_carry", 0 0, L_011CF338; 1 drivers
v011CC4F0_0 .net "add1_sum", 0 0, L_011CF2C8; 1 drivers
v011CC180_0 .net "add2_carry", 0 0, L_011CF5D8; 1 drivers
v011CBE10_0 .net "b", 0 0, L_011CF670; 1 drivers
v011CBA48_0 .net "carry_in", 0 0, L_011CFD50; 1 drivers
v011CBEC0_0 .net "carry_out", 0 0, L_011CDC80; 1 drivers
v011CBF18_0 .net "sum", 0 0, L_011CEFF0; 1 drivers
S_0118B100 .scope module, "add1" "half_adder" 4 23, 5 5, S_0118BF58;
 .timescale 0 0;
L_011CF2C8 .functor XOR 1, L_011CFC48, L_011CF670, C4<0>, C4<0>;
L_011CF338 .functor AND 1, L_011CFC48, L_011CF670, C4<1>, C4<1>;
v011CBCB0_0 .alias "a", 0 0, v011CC440_0;
v011CC338_0 .alias "b", 0 0, v011CBE10_0;
v011CC0D0_0 .alias "carry", 0 0, v011CC128_0;
v011CBDB8_0 .alias "sum", 0 0, v011CC4F0_0;
S_0118BFE0 .scope module, "add2" "half_adder" 4 24, 5 5, S_0118BF58;
 .timescale 0 0;
L_011CEFF0 .functor XOR 1, L_011CF2C8, L_011CFD50, C4<0>, C4<0>;
L_011CF5D8 .functor AND 1, L_011CF2C8, L_011CFD50, C4<1>, C4<1>;
v011CC078_0 .alias "a", 0 0, v011CC4F0_0;
v011CBC58_0 .alias "b", 0 0, v011CBA48_0;
v011CC230_0 .alias "carry", 0 0, v011CC180_0;
v011CBBA8_0 .alias "sum", 0 0, v011CBF18_0;
S_0118C7D8 .scope generate, "generar_full_adder[5]" "generar_full_adder[5]" 3 19, 3 19, S_0118BE48;
 .timescale 0 0;
P_01190CAC .param/l "i" 3 19, +C4<0101>;
S_0118C4A8 .scope module, "full_adder" "full_adder_structural" 3 20, 4 16, S_0118C7D8;
 .timescale 0 0;
L_011D0918 .functor OR 1, L_011CDAC0, L_011D0C60, C4<0>, C4<0>;
v011CBB50_0 .net "a", 0 0, L_011CF778; 1 drivers
v011CC3E8_0 .net "add1_carry", 0 0, L_011CDAC0; 1 drivers
v011CBD08_0 .net "add1_sum", 0 0, L_011CDD28; 1 drivers
v011CBFC8_0 .net "add2_carry", 0 0, L_011D0C60; 1 drivers
v011CC390_0 .net "b", 0 0, L_011CFA90; 1 drivers
v011CBD60_0 .net "carry_in", 0 0, L_011CFA38; 1 drivers
v011CC020_0 .net "carry_out", 0 0, L_011D0918; 1 drivers
v011CC2E0_0 .net "sum", 0 0, L_011CEF80; 1 drivers
S_0118BD38 .scope module, "add1" "half_adder" 4 23, 5 5, S_0118C4A8;
 .timescale 0 0;
L_011CDD28 .functor XOR 1, L_011CF778, L_011CFA90, C4<0>, C4<0>;
L_011CDAC0 .functor AND 1, L_011CF778, L_011CFA90, C4<1>, C4<1>;
v011CBC00_0 .alias "a", 0 0, v011CBB50_0;
v011CC288_0 .alias "b", 0 0, v011CC390_0;
v011CBE68_0 .alias "carry", 0 0, v011CC3E8_0;
v011CBAF8_0 .alias "sum", 0 0, v011CBD08_0;
S_0118BB18 .scope module, "add2" "half_adder" 4 24, 5 5, S_0118C4A8;
 .timescale 0 0;
L_011CEF80 .functor XOR 1, L_011CDD28, L_011CFA38, C4<0>, C4<0>;
L_011D0C60 .functor AND 1, L_011CDD28, L_011CFA38, C4<1>, C4<1>;
v01196AC0_0 .alias "a", 0 0, v011CBD08_0;
v011CBF70_0 .alias "b", 0 0, v011CBD60_0;
v011CC498_0 .alias "carry", 0 0, v011CBFC8_0;
v011CBAA0_0 .alias "sum", 0 0, v011CC2E0_0;
S_0118BCB0 .scope generate, "generar_full_adder[6]" "generar_full_adder[6]" 3 19, 3 19, S_0118BE48;
 .timescale 0 0;
P_01190C4C .param/l "i" 3 19, +C4<0110>;
S_0118C640 .scope module, "full_adder" "full_adder_structural" 3 20, 4 16, S_0118BCB0;
 .timescale 0 0;
L_011D0B80 .functor OR 1, L_011D0988, L_011D0B10, C4<0>, C4<0>;
v01196490_0 .net "a", 0 0, L_011CFE00; 1 drivers
v011964E8_0 .net "add1_carry", 0 0, L_011D0988; 1 drivers
v011969B8_0 .net "add1_sum", 0 0, L_011D08A8; 1 drivers
v01196540_0 .net "add2_carry", 0 0, L_011D0B10; 1 drivers
v011966F8_0 .net "b", 0 0, L_011CF6C8; 1 drivers
v011968B0_0 .net "carry_in", 0 0, L_011CFF60; 1 drivers
v01196908_0 .net "carry_out", 0 0, L_011D0B80; 1 drivers
v01196A68_0 .net "sum", 0 0, L_011D0AD8; 1 drivers
S_0118BA08 .scope module, "add1" "half_adder" 4 23, 5 5, S_0118C640;
 .timescale 0 0;
L_011D08A8 .functor XOR 1, L_011CFE00, L_011CF6C8, C4<0>, C4<0>;
L_011D0988 .functor AND 1, L_011CFE00, L_011CF6C8, C4<1>, C4<1>;
v01196120_0 .alias "a", 0 0, v01196490_0;
v011963E0_0 .alias "b", 0 0, v011966F8_0;
v01196858_0 .alias "carry", 0 0, v011964E8_0;
v01196438_0 .alias "sum", 0 0, v011969B8_0;
S_0118C6C8 .scope module, "add2" "half_adder" 4 24, 5 5, S_0118C640;
 .timescale 0 0;
L_011D0AD8 .functor XOR 1, L_011D08A8, L_011CFF60, C4<0>, C4<0>;
L_011D0B10 .functor AND 1, L_011D08A8, L_011CFF60, C4<1>, C4<1>;
v01196750_0 .alias "a", 0 0, v011969B8_0;
v01196330_0 .alias "b", 0 0, v011968B0_0;
v01196A10_0 .alias "carry", 0 0, v01196540_0;
v01196070_0 .alias "sum", 0 0, v01196A68_0;
S_0118C0F0 .scope generate, "generar_full_adder[7]" "generar_full_adder[7]" 3 19, 3 19, S_0118BE48;
 .timescale 0 0;
P_01190EAC .param/l "i" 3 19, +C4<0111>;
S_0118C398 .scope module, "full_adder" "full_adder_structural" 3 20, 4 16, S_0118C0F0;
 .timescale 0 0;
L_011D0870 .functor OR 1, L_011D0790, L_011D0BF0, C4<0>, C4<0>;
v011960C8_0 .net "a", 0 0, L_011D0118; 1 drivers
v01196388_0 .net "add1_carry", 0 0, L_011D0790; 1 drivers
v011965F0_0 .net "add1_sum", 0 0, L_011D0BB8; 1 drivers
v011961D0_0 .net "add2_carry", 0 0, L_011D0BF0; 1 drivers
v01196018_0 .net "b", 0 0, L_011CFE58; 1 drivers
v01196598_0 .net "carry_in", 0 0, L_011CFBF0; 1 drivers
v01196800_0 .net "carry_out", 0 0, L_011D0870; 1 drivers
v011966A0_0 .net "sum", 0 0, L_011D07C8; 1 drivers
S_0118C178 .scope module, "add1" "half_adder" 4 23, 5 5, S_0118C398;
 .timescale 0 0;
L_011D0BB8 .functor XOR 1, L_011D0118, L_011CFE58, C4<0>, C4<0>;
L_011D0790 .functor AND 1, L_011D0118, L_011CFE58, C4<1>, C4<1>;
v011962D8_0 .alias "a", 0 0, v011960C8_0;
v011967A8_0 .alias "b", 0 0, v01196018_0;
v01196228_0 .alias "carry", 0 0, v01196388_0;
v01196648_0 .alias "sum", 0 0, v011965F0_0;
S_0118C420 .scope module, "add2" "half_adder" 4 24, 5 5, S_0118C398;
 .timescale 0 0;
L_011D07C8 .functor XOR 1, L_011D0BB8, L_011CFBF0, C4<0>, C4<0>;
L_011D0BF0 .functor AND 1, L_011D0BB8, L_011CFBF0, C4<1>, C4<1>;
v01196BC8_0 .alias "a", 0 0, v011965F0_0;
v01196960_0 .alias "b", 0 0, v01196598_0;
v01196280_0 .alias "carry", 0 0, v011961D0_0;
v01196178_0 .alias "sum", 0 0, v011966A0_0;
S_0118BDC0 .scope module, "full_adder_behavioral" "full_adder_behavioral" 4 37;
 .timescale 0 0;
v011CE908_0 .net "a", 0 0, C4<z>; 0 drivers
v011CE178_0 .net "b", 0 0, C4<z>; 0 drivers
v011CE1D0_0 .net "carry_in", 0 0, C4<z>; 0 drivers
v011CE228_0 .var "carry_out", 0 0;
v011CE490_0 .var "sum", 0 0;
E_01190788 .event edge, v011CE908_0, v011CE178_0, v011CE1D0_0;
S_0118C530 .scope module, "full_adder_dataflow" "full_adder_dataflow" 4 29;
 .timescale 0 0;
L_011D09F8 .functor XOR 1, C4<z>, C4<z>, C4<0>, C4<0>;
L_011D0A30 .functor XOR 1, L_011D09F8, C4<z>, C4<0>, C4<0>;
L_011D06B0 .functor AND 1, C4<z>, C4<z>, C4<1>, C4<1>;
L_011D0DB0 .functor XOR 1, C4<z>, C4<z>, C4<0>, C4<0>;
L_011D0D78 .functor AND 1, C4<z>, L_011D0DB0, C4<1>, C4<1>;
L_011CDA50 .functor OR 1, L_011D06B0, L_011D0D78, C4<0>, C4<0>;
v011CE4E8_0 .net *"_s0", 0 0, L_011D09F8; 1 drivers
v011CDE60_0 .net *"_s4", 0 0, L_011D06B0; 1 drivers
v011CE280_0 .net *"_s6", 0 0, L_011D0DB0; 1 drivers
v011CE388_0 .net *"_s8", 0 0, L_011D0D78; 1 drivers
v011CE598_0 .net "a", 0 0, C4<z>; 0 drivers
v011CE5F0_0 .net "b", 0 0, C4<z>; 0 drivers
v011CDF10_0 .net "carry_in", 0 0, C4<z>; 0 drivers
v011CDF68_0 .net "carry_out", 0 0, L_011CDA50; 1 drivers
v011CE330_0 .net "sum", 0 0, L_011D0A30; 1 drivers
S_0118C310 .scope module, "half_adder_behavioral" "half_adder_behavioral" 5 21;
 .timescale 0 0;
v011CDFC0_0 .net "a", 0 0, C4<z>; 0 drivers
v011CE648_0 .net "b", 0 0, C4<z>; 0 drivers
v011CE6A0_0 .var "carry", 0 0;
v011CEA10_0 .var "sum", 0 0;
E_011907C8 .event edge, v011CE648_0, v011CDFC0_0;
S_0118C5B8 .scope module, "half_adder_dataflow" "half_adder_dataflow" 5 13;
 .timescale 0 0;
L_011D0EB8 .functor XOR 1, C4<z>, C4<z>, C4<0>, C4<0>;
L_011D0EF0 .functor AND 1, C4<z>, C4<z>, C4<1>, C4<1>;
v011CECD0_0 .net "a", 0 0, C4<z>; 0 drivers
v011CEB18_0 .net "b", 0 0, C4<z>; 0 drivers
v011CE9B8_0 .net "carry", 0 0, L_011D0EF0; 1 drivers
v011CEA68_0 .net "sum", 0 0, L_011D0EB8; 1 drivers
    .scope S_0118C068;
T_0 ;
    %vpi_call 2 19 "$dumpfile", "./adder_nbit/adder_nbit.vcd";
    %vpi_call 2 20 "$dumpvars", 1'sb0, S_0118C068;
    %set/v v011CE8B0_0, 0, 8;
    %movi 8, 5, 8;
    %set/v v011CE3E0_0, 8, 8;
    %set/v v011CE750_0, 0, 1;
    %delay 1, 0;
    %vpi_call 2 24 "$display", "a=%d, b=%d, sum=%d, carry=%b", v011CE8B0_0, v011CE3E0_0, v011CE7A8_0, v011CE800_0;
    %movi 8, 10, 8;
    %set/v v011CE8B0_0, 8, 8;
    %movi 8, 5, 8;
    %set/v v011CE3E0_0, 8, 8;
    %set/v v011CE750_0, 0, 1;
    %delay 1, 0;
    %vpi_call 2 27 "$display", "a=%d, b=%d, sum=%d, carry=%b", v011CE8B0_0, v011CE3E0_0, v011CE7A8_0, v011CE800_0;
    %movi 8, 100, 8;
    %set/v v011CE8B0_0, 8, 8;
    %movi 8, 5, 8;
    %set/v v011CE3E0_0, 8, 8;
    %set/v v011CE750_0, 0, 1;
    %delay 1, 0;
    %vpi_call 2 30 "$display", "a=%d, b=%d, sum=%d, carry=%b", v011CE8B0_0, v011CE3E0_0, v011CE7A8_0, v011CE800_0;
    %end;
    .thread T_0;
    .scope S_0118BDC0;
T_1 ;
    %wait E_01190788;
    %load/v 8, v011CE908_0, 1;
    %load/v 9, v011CE178_0, 1;
    %xor 8, 9, 1;
    %load/v 9, v011CE1D0_0, 1;
    %xor 8, 9, 1;
    %set/v v011CE490_0, 8, 1;
    %load/v 8, v011CE908_0, 1;
    %load/v 9, v011CE178_0, 1;
    %and 8, 9, 1;
    %load/v 9, v011CE1D0_0, 1;
    %load/v 10, v011CE908_0, 1;
    %load/v 11, v011CE178_0, 1;
    %xor 10, 11, 1;
    %and 9, 10, 1;
    %or 8, 9, 1;
    %set/v v011CE228_0, 8, 1;
    %jmp T_1;
    .thread T_1, $push;
    .scope S_0118C310;
T_2 ;
    %wait E_011907C8;
    %load/v 8, v011CDFC0_0, 1;
    %load/v 9, v011CE648_0, 1;
    %xor 8, 9, 1;
    %set/v v011CEA10_0, 8, 1;
    %load/v 8, v011CDFC0_0, 1;
    %load/v 9, v011CE648_0, 1;
    %and 8, 9, 1;
    %set/v v011CE6A0_0, 8, 1;
    %jmp T_2;
    .thread T_2, $push;
# The file index is used to find the file name in the following table.
:file_names 6;
    "N/A";
    "<interactive>";
    ".\adder_nbit\adder_nbit_tb.v";
    "././adder_nbit/adder_nbit.v";
    "././full_adder/full_adder.v";
    "././half_adder/half_adder.v";