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hdl-projects/half_adder/readme.md

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2026-02-28 21:59:55 +01:00
1. Compilar el testbench
`
iverilog -o .\half_adder_tb.vvp .\half_adder_tb.v
`
2. Ejecutar simulacion del testbench
`
vvp .\half_adder_tb.vvp
`
3. Visualizar ondas
`
gtkwave .\half_adder.vcd
`