134 lines
1.4 KiB
Plaintext
134 lines
1.4 KiB
Plaintext
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$date
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Sat Feb 28 21:00:53 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module basic_alu_tb $end
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$var wire 1 ! carry $end
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$var wire 1 " negative $end
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$var wire 16 # result [15:0] $end
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$var wire 1 $ zero $end
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$var reg 16 % a [15:0] $end
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$var reg 16 & b [15:0] $end
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$var reg 4 ' opcode [3:0] $end
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$scope module alu $end
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$var wire 16 ( a [15:0] $end
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$var wire 16 ) b [15:0] $end
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$var wire 1 " negative $end
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$var wire 4 * opcode [3:0] $end
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$var wire 1 $ zero $end
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$var reg 1 + carry $end
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$var reg 16 , result [15:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b11001 ,
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0+
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b0 *
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b101 )
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b10100 (
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b0 '
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b101 &
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b10100 %
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0$
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b11001 #
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0"
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0!
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$end
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#1
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b1111 ,
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b1111 #
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b1 '
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b1 *
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#2
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1+
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1!
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b0 ,
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1$
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b0 #
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b1 &
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b1 )
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b1111111111111111 %
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b1111111111111111 (
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b0 '
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b0 *
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#3
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1"
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b1111111111110001 ,
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0$
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b1111111111110001 #
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1+
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1!
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b10100 &
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b10100 )
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b101 %
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b101 (
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b1 '
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b1 *
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#4
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0"
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b111110100 ,
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b111110100 #
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0+
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0!
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b101 &
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b101 )
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b1100100 %
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b1100100 (
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b10 '
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b10 *
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#5
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b10100 ,
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b10100 #
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b11 '
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b11 *
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#6
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b111100000000 ,
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b111100000000 #
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b111111110000 &
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b111111110000 )
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b1111111100000000 %
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b1111111100000000 (
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b100 '
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b100 *
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#7
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1"
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b1111111111110000 ,
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b1111111111110000 #
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b101 '
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b101 *
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#8
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b1111111111111111 ,
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b1111111111111111 #
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b0 &
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b0 )
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b0 %
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b0 (
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b110 '
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b110 *
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#9
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b1111000011110000 ,
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b1111000011110000 #
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b111111110000 &
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b111111110000 )
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b1111111100000000 %
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b1111111100000000 (
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b1001 '
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b1001 *
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#10
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b1111111111111111 ,
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b1111111111111111 #
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b0 &
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b0 )
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b1 %
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b1 (
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b1011 '
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b1011 *
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#11
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