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hdl-projects/counter/counter.v

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2026-03-01 01:42:33 +01:00
/*
Contador
*/
module counter #(parameter N = 8) (
input clk,
input rst,
input write,
input [N-1:0] write_value,
output reg [N-1:0] count
);
always @(posedge clk or posedge rst) begin
if (rst) count <= 0;
else if (write) count <= write_value;
else count <= count + 1;
end
endmodule