38 lines
951 B
Coq
38 lines
951 B
Coq
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/*
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Registros
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*/
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module register_file #(
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parameter REGS = 16,
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parameter W = 16
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) (
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input clk,
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input rst,
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// Puerto escritura
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input [$clog2(REGS)-1:0] wr_addr,
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input [W-1:0] wr_data,
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input wr_en,
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// Puerto lectura 1
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input [$clog2(REGS)-1:0] rd_addr1,
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output [W-1:0] rd_data1,
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// Puerto lectura 2
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input [$clog2(REGS)-1:0] rd_addr2,
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output [W-1:0] rd_data2
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);
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reg [W-1:0] regs [0:REGS-1];
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// Lectura combinacional
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assign rd_data1 = regs[rd_addr1];
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assign rd_data2 = regs[rd_addr2];
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// Escritura sincrona
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integer i;
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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for (i = 0; i < REGS; i = i + 1)
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regs[i] <= 0;
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end else if (wr_en) begin
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regs[wr_addr] <= wr_data;
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end
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end
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endmodule
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