60 lines
2.0 KiB
Coq
60 lines
2.0 KiB
Coq
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/*
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Registros
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*/
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`include "./register_file/register_file.v"
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module register_file_tb;
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reg clk, rst, wr_en;
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reg [3:0] wr_addr;
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reg [15:0] wr_data;
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reg [3:0] rd_addr1, rd_addr2;
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wire [15:0] rd_value1, rd_value2;
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register_file register(
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.clk(clk),
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.rst(rst),
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.wr_addr(wr_addr),
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.wr_data(wr_data),
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.wr_en(wr_en),
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.rd_addr1(rd_addr1),
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.rd_data1(rd_value1),
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.rd_addr2(rd_addr2),
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.rd_data2(rd_value2)
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);
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initial clk = 0;
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always #5 clk = ~clk;
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initial begin
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$dumpfile("register_file/register_file.vcd");
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$dumpvars(0, register_file_tb);
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rst = 1; wr_en = 0; wr_addr = 0; wr_data = 0;
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rd_addr1 = 0; rd_addr2 = 0;
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@(posedge clk);
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$display("rst=%b, wr_en=%b, wr_add=%d, wr_data=%d", rst, wr_en, wr_addr, wr_data);
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$display("rd_addr1=%d, rd_addr2=%d, rd_value1=%d, rd_value2=%d", rd_addr1, rd_addr2, rd_value1, rd_value2);
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rst = 0;
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@(posedge clk);
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$display("rst=%b, wr_en=%b, wr_add=%d, wr_data=%d", rst, wr_en, wr_addr, wr_data);
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$display("rd_addr1=%d, rd_addr2=%d, rd_value1=%d, rd_value2=%d", rd_addr1, rd_addr2, rd_value1, rd_value2);
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wr_en = 1; wr_addr = 1; wr_data = 16'hBEEF;
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@(posedge clk);
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$display("rst=%b, wr_en=%b, wr_add=%d, wr_data=%d", rst, wr_en, wr_addr, wr_data);
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$display("rd_addr1=%d, rd_addr2=%d, rd_value1=%d, rd_value2=%d", rd_addr1, rd_addr2, rd_value1, rd_value2);
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wr_en = 0;
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@(posedge clk);
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$display("rst=%b, wr_en=%b, wr_add=%d, wr_data=%d", rst, wr_en, wr_addr, wr_data);
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$display("rd_addr1=%d, rd_addr2=%d, rd_value1=%d, rd_value2=%d", rd_addr1, rd_addr2, rd_value1, rd_value2);
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rd_addr1 = 1;
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@(posedge clk);
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$display("rst=%b, wr_en=%b, wr_add=%d, wr_data=%d", rst, wr_en, wr_addr, wr_data);
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$display("rd_addr1=%d, rd_addr2=%d, rd_value1=%d, rd_value2=%d", rd_addr1, rd_addr2, rd_value1, rd_value2);
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repeat(100) @(posedge clk);
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$finish;
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end
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endmodule
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