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hdl-projects/fsm_traffic/fsm_traffic.v

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2026-03-01 05:00:05 +01:00
/*
fsm_traffic
*/
module fsm_traffic (
input clk,
input rst,
output red_led,
output green_led,
output yellow_led
);
localparam RED = 2'b00;
localparam GREEN = 2'b01;
localparam YELLOW = 2'b10;
reg[1:0] state, next_state;
reg[7:0] timer;
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= RED;
timer <= 3;
end
else if (timer == 0) begin
state <= next_state;
case (next_state)
RED: timer <= 3;
YELLOW: timer <= 1;
GREEN: timer <= 2;
default: timer <= 3;
endcase
end
else timer <= timer - 1;
end
always @(*) begin
case (state)
RED: next_state = GREEN;
YELLOW: next_state = RED;
GREEN: next_state = YELLOW;
default: next_state = RED;
endcase
end
assign red_led = state == RED;
assign green_led = state == GREEN;
assign yellow_led = state == YELLOW;
endmodule