52 lines
467 B
Plaintext
52 lines
467 B
Plaintext
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$date
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Sat Feb 28 20:27:18 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module half_adder_tb $end
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$var wire 1 ! carry $end
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$var wire 1 " sum $end
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$var reg 1 # a $end
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$var reg 1 $ b $end
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$scope module add1 $end
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$var wire 1 % a $end
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$var wire 1 & b $end
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$var wire 1 ! carry $end
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$var wire 1 " sum $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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0&
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0%
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0$
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0#
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0"
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0!
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$end
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#1
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1"
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1$
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1&
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#2
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0$
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0&
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1#
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1%
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#3
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0"
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1!
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1$
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1&
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#4
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0!
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0$
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0&
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0#
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0%
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