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hdl-projects/mux_demux/mux_demux_tb.v

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2026-03-01 01:02:35 +01:00
`include "./mux_demux/mux_demux.v"
module mux_demux_tb();
reg [7:0] a, b;
reg sel;
wire [7:0] out, _a, _b;
mux_Nn1 #(.DATA_W(8), .SEL_W(1)) mux (
.in({b, a}),
.sel(sel),
.out(out)
);
demux_1n2 demux (
.in(out),
.sel(sel),
.a(_a),
.b(_b)
);
initial begin
$dumpfile("./mux_demux/mux_demux.vcd");
$dumpvars(0, mux_demux_tb);
a = 20; b = 5; sel = 0;
#1
$display("a=%d, b=%d, sel=%b out=%d _a=%d, _b=%d", a, b, sel, out, _a, _b);
a = 21; b = 5; sel = 0;
#1
$display("a=%d, b=%d, sel=%b out=%d _a=%d, _b=%d", a, b, sel, out, _a, _b);
a = 22; b = 5; sel = 0;
#1
$display("a=%d, b=%d, sel=%b out=%d _a=%d, _b=%d", a, b, sel, out, _a, _b);
a = 22; b = 5; sel = 1;
#1
$display("a=%d, b=%d, sel=%b out=%d _a=%d, _b=%d", a, b, sel, out, _a, _b);
a = 22; b = 15; sel = 1;
#1
$display("a=%d, b=%d, sel=%b out=%d _a=%d, _b=%d", a, b, sel, out, _a, _b);
end
endmodule