24 lines
513 B
Coq
24 lines
513 B
Coq
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/*
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Ram Sincrona
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*/
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module ram #(
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parameter DEPTH = 256, // posiciones
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parameter W = 16 // bits por posicion
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) (
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input clk,
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input wr_en,
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input [$clog2(DEPTH)-1:0] addr,
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input [W-1:0] wr_data,
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output reg [W-1:0] rd_data
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);
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reg [W-1:0] mem [0:DEPTH-1];
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always @(posedge clk) begin
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if (wr_en)
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mem[addr] <= wr_data;
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else
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rd_data <= mem[addr];
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end
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endmodule
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