56 lines
1.5 KiB
Coq
56 lines
1.5 KiB
Coq
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/*
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Basic ALU 16bit
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inputs: opcode, a, b
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outputs: result, zero, carry, negative
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opcode[3:0] | Operación
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-------------------------------
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0x0 | ADD
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0x1 | SUB
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0x2 | MUL
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0x3 | DIV
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0x4 | AND
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0x5 | OR
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0x6 | NOT
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0x7 | NAND
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0x8 | NOR
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0x9 | XOR
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0xA | XNOR
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0xB | NEG
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*/
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module basic_alu (
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input [3:0] opcode,
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input [15:0] a,
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input [15:0] b,
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output reg [15:0] result,
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output zero,
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output reg carry,
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output negative
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);
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always @(*) begin
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carry = 0;
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case (opcode)
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4'h0: {carry, result} = a + b; // ADD
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4'h1: {carry, result} = a - b; // SUB
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4'h2: result = a * b; // MUL
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4'h3: result = a / b; // DIV
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4'h4: result = a & b; // AND
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4'h5: result = a | b; // OR
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4'h6: result = ~a; // NOT
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4'h7: result = ~(a & b); // NAND
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4'h8: result = ~(a | b); // NOR
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4'h9: result = a ^ b; // XOR
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4'hA: result = ~(a ^ b); // XNOR
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4'hB: result = ~a + 1; // NEG
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default: result = 0;
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endcase
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end
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assign zero = result == 0;
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assign negative = result[15];
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endmodule
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