diff --git a/counter/counter.v b/counter/counter.v new file mode 100644 index 0000000..ca65ea1 --- /dev/null +++ b/counter/counter.v @@ -0,0 +1,18 @@ +/* + Contador +*/ + +module counter #(parameter N = 8) ( + input clk, + input rst, + input write, + input [N-1:0] write_value, + output reg [N-1:0] count +); + + always @(posedge clk or posedge rst) begin + if (rst) count <= 0; + else if (write) count <= write_value; + else count <= count + 1; + end +endmodule \ No newline at end of file diff --git a/counter/counter_tb.v b/counter/counter_tb.v new file mode 100644 index 0000000..d9dfa4f --- /dev/null +++ b/counter/counter_tb.v @@ -0,0 +1,44 @@ +`include "./counter/counter.v" + +module counter_tb; + reg clk, rst, write_enable; + reg [15:0] write_value; + wire [15:0] count; + + counter #(.N(16)) cnt( + .clk(clk), + .rst(rst), + .write(write_enable), + .write_value(write_value), + .count(count) + ); + + initial clk = 0; + always #5 clk = ~clk; + + initial begin + $dumpfile("./counter/counter.vcd"); + $dumpvars(0, counter_tb); + + rst = 1; write_enable = 0; write_value = 0; + @(posedge clk); #1 + rst = 0; + + // Contar 20 ciclos + repeat(20) @(posedge clk); + #1 $display("despues de 20 ciclos: count=%0d", count); + + // Load a 200 + write_enable = 1; write_value = 200; + @(posedge clk); #1 + write_enable = 0; + $display("tras load 200: count=%0d", count); + + // Contar hasta overflow (56 ciclos llega a 255 y desborda a 0) + repeat(60) @(posedge clk); + #1 $display("tras 60 ciclos mas: count=%0d", count); + + $finish; + end + +endmodule \ No newline at end of file diff --git a/roadmap.md b/roadmap.md index 57f25ac..c7b0d84 100644 --- a/roadmap.md +++ b/roadmap.md @@ -348,7 +348,7 @@ gtkwave modulo.vcd - [x] Fase 1.4 — Mux / Demux - [x] Fase 1.5 — Decoder / Encoder - [x] Fase 2.1 — Flip-Flop D y registro -- [ ] Fase 2.2 — Contador +- [x] Fase 2.2 — Contador - [ ] Fase 2.3 — Shift Register - [ ] Fase 2.4 — Register File - [ ] Fase 3.1 — RAM sincrona