From 5cc4b5adf4ed9f26c5eb269962bf7c38b9660e34 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jose=20Luis=20Monta=C3=B1es=20Ojados?=
 <joseluis@greenest.ai>
Date: Sun, 1 Mar 2026 02:22:06 +0100
Subject: [PATCH] add shift_register

---
 roadmap.md                         |  2 +-
 shift_register/shift_register.v    | 24 +++++++++++++++
 shift_register/shift_register_tb.v | 48 ++++++++++++++++++++++++++++++
 3 files changed, 73 insertions(+), 1 deletion(-)
 create mode 100644 shift_register/shift_register.v
 create mode 100644 shift_register/shift_register_tb.v

diff --git a/roadmap.md b/roadmap.md
index c7b0d84..6efa857 100644
--- a/roadmap.md
+++ b/roadmap.md
@@ -349,7 +349,7 @@ gtkwave modulo.vcd
 - [x] Fase 1.5 — Decoder / Encoder
 - [x] Fase 2.1 — Flip-Flop D y registro
 - [x] Fase 2.2 — Contador
-- [ ] Fase 2.3 — Shift Register
+- [x] Fase 2.3 — Shift Register
 - [ ] Fase 2.4 — Register File
 - [ ] Fase 3.1 — RAM sincrona
 - [ ] Fase 3.2 — ROM
diff --git a/shift_register/shift_register.v b/shift_register/shift_register.v
new file mode 100644
index 0000000..6cbc208
--- /dev/null
+++ b/shift_register/shift_register.v
@@ -0,0 +1,24 @@
+module shift_register #(parameter N = 8) (
+    input clk,
+    input rst,
+    input load,
+    input shift_en,
+    input dir,
+    input serial_in,
+    input [N-1:0] parallel_in,
+    output reg [N-1:0] q,
+    output serial_out
+);
+
+    assign serial_out = dir ? q[0] : q[N-1];
+
+    always @(posedge clk or posedge rst) begin
+        if (rst) q <= 0;
+        else if (load) q <= parallel_in;
+        else if (shift_en) begin
+            if (dir == 0) q <= {q[N-2:0], serial_in};
+            else q <= {serial_in, q[N-1:1]};
+        end
+    end
+
+endmodule
\ No newline at end of file
diff --git a/shift_register/shift_register_tb.v b/shift_register/shift_register_tb.v
new file mode 100644
index 0000000..fcdfca6
--- /dev/null
+++ b/shift_register/shift_register_tb.v
@@ -0,0 +1,48 @@
+`include "./shift_register/shift_register.v"
+
+module shift_register_tb;
+    reg clk, rst, load, shift_en, dir, serial_in;
+    reg [7:0] parallel_in;
+    wire [7:0] q;
+    wire serial_out;
+
+    shift_register register(
+        .clk(clk),
+        .rst(rst),
+        .load(load),
+        .shift_en(shift_en),
+        .dir(dir),
+        .serial_in(serial_in),
+        .parallel_in(parallel_in),
+        .q(q),
+        .serial_out(serial_out)
+    );
+
+    initial clk = 0;
+    always #5 clk = ~clk;
+
+    initial begin
+        $dumpfile("./shift_register/shift_register.vcd");
+        $dumpvars(0, shift_register_tb);
+
+        rst = 1; load = 0; shift_en = 1; dir = 0; serial_in = 0;
+        @(posedge clk);
+
+        $display("rst=%b, load=%b, shift_en=%b, dir=%b, serial_in=%b, q=%b", rst, load, shift_en, dir, serial_in, q);
+
+        rst = 0; load = 1; parallel_in = 64;
+        @(posedge clk);
+
+        $display("rst=%b, load=%b, shift_en=%b, dir=%b, serial_in=%b, q=%b", rst, load, shift_en, dir, serial_in, q);
+
+        load = 0; serial_in = 1;
+        @(posedge clk);
+        $display("rst=%b, load=%b, shift_en=%b, dir=%b, serial_in=%b, q=%b", rst, load, shift_en, dir, serial_in, q);
+
+        repeat(10) @(posedge clk);
+        $display("rst=%b, load=%b, shift_en=%b, dir=%b, serial_in=%b, q=%b", rst, load, shift_en, dir, serial_in, q);
+
+        $finish;
+    end
+
+endmodule
\ No newline at end of file