From 6df702470720313c13a5b860d6e5fc27f7820180 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jose=20Luis=20Monta=C3=B1es=20Ojados?=
 <joseluis@greenest.ai>
Date: Sun, 1 Mar 2026 04:28:56 +0100
Subject: [PATCH] add stack

---
 roadmap.md       |  2 +-
 stack/stack.v    | 33 +++++++++++++++++++++++++
 stack/stack_tb.v | 63 ++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 97 insertions(+), 1 deletion(-)
 create mode 100644 stack/stack.v
 create mode 100644 stack/stack_tb.v

diff --git a/roadmap.md b/roadmap.md
index 0ff6a91..046c0f8 100644
--- a/roadmap.md
+++ b/roadmap.md
@@ -353,7 +353,7 @@ gtkwave modulo.vcd
 - [x] Fase 2.4 — Register File
 - [x] Fase 3.1 — RAM sincrona
 - [x] Fase 3.2 — ROM
-- [ ] Fase 3.3 — Stack
+- [x] Fase 3.3 — Stack
 - [ ] Fase 4.1 — FSM Semaforo
 - [ ] Fase 4.2 — UART TX
 - [ ] Fase 5.1 — Fetch Unit
diff --git a/stack/stack.v b/stack/stack.v
new file mode 100644
index 0000000..753a13e
--- /dev/null
+++ b/stack/stack.v
@@ -0,0 +1,33 @@
+/*
+    Stack
+*/
+
+module stack #(
+    parameter DEPTH = 256,
+    parameter W     = 16
+) (
+    input               clk,
+    input               rst,
+    input               push,
+    input               pop,
+    input [W-1:0]       value,
+    output reg [W-1:0]  out
+);
+    reg [W-1:0] mem [0:DEPTH-1];
+    reg [$clog2(DEPTH):0] sp;  // bit extra para detectar overflow
+
+    wire full  = (sp == DEPTH);
+    wire empty = (sp == 0);
+
+    always @(posedge clk or posedge rst) begin
+        if (rst) begin
+            sp <= 0;
+        end else if (push && !full) begin
+            mem[sp] <= value;
+            sp <= sp + 1;
+        end else if (pop && !empty) begin
+            out <= mem[sp - 1];
+            sp <= sp - 1;
+        end
+    end
+endmodule
\ No newline at end of file
diff --git a/stack/stack_tb.v b/stack/stack_tb.v
new file mode 100644
index 0000000..083718c
--- /dev/null
+++ b/stack/stack_tb.v
@@ -0,0 +1,63 @@
+/*
+    Stack testbench
+*/
+
+`include "stack/stack.v"
+
+module stack_tb;
+    reg clk, rst, push, pop;
+    reg[15:0]   in;
+    wire [15:0] out;
+
+    stack stack1(
+        .clk(clk),
+        .rst(rst),
+        .push(push),
+        .pop(pop),
+        .value(in),
+        .out(out)
+    );
+
+    initial clk = 0;
+    always #5 clk = ~clk;
+
+    initial begin
+        $dumpfile("stack/stack.vcd");
+        $dumpvars(0, stack_tb);
+
+        rst = 1; push = 0; pop = 0; in = 0;
+        @(posedge clk); #1
+        rst = 0;
+        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
+
+        push = 1; pop = 0; in = 69;
+        @(posedge clk); #1
+        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
+
+        push = 1; pop = 0; in = 40;
+        @(posedge clk); #1
+        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
+
+        push = 0; pop = 0; in = 0;
+        @(posedge clk); #1
+        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
+
+        push = 0; pop = 1; in = 0;
+        @(posedge clk); #1
+        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
+        push = 0; pop = 0; in = 0;
+        @(posedge clk); #1
+        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
+
+
+        push = 0; pop = 1; in = 0;
+        @(posedge clk); #1 
+        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
+        push = 0; pop = 0; in = 0;
+        @(posedge clk); #1
+        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
+
+
+        $finish;
+    end
+endmodule
\ No newline at end of file