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mux_demux

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Jose Luis Montañes Ojados
2026-03-01 01:02:35 +01:00
parent 838ee4c0ae
commit a1a95b50ab
2 changed files with 134 additions and 0 deletions
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91
mux_demux/mux_demux.v
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@@ -31,4 +31,95 @@ module demux_1n2 #(parameter N = 8) (
);
assign a = sel ? 0 : in;
assign b = sel ? in : 0;
endmodule
module mux_4n1 #(parameter N = 8) (
input [N-1:0] a,
input [N-1:0] b,
input [N-1:0] c,
input [N-1:0] d,
input [1:0] sel,
output reg [N-1:0] out
);
always @(*) begin
case (sel)
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
2'b11: out = d;
default: out = a;
endcase
end
endmodule
module demux_1n4 #(parameter N = 8) (
input [N-1:0] in,
input [1:0] sel,
output reg [N-1:0] a,
output reg [N-1:0] b,
output reg [N-1:0] c,
output reg [N-1:0] d
);
always @(*) begin
a = 0; b = 0; c = 0; d = 0;
case (sel)
2'b00: a = in;
2'b01: b = in;
2'b10: c = in;
2'b11: d = in;
default: a = in;
endcase
end
endmodule
module mux_8n1 #(parameter N = 8) (
input [N-1:0] a,
input [N-1:0] b,
input [N-1:0] c,
input [N-1:0] d,
input [N-1:0] e,
input [N-1:0] f,
input [N-1:0] g,
input [N-1:0] h,
input [2:0] sel,
output reg [N-1:0] out
);
always @(*) begin
case (sel)
3'b000: out = a;
3'b001: out = b;
3'b010: out = c;
3'b011: out = d;
3'b100: out = e;
3'b101: out = f;
3'b110: out = g;
3'b111: out = h;
default: out = a;
endcase
end
endmodule
module mux_Nn1 #(
parameter DATA_W = 8, // bits por dato
parameter SEL_W = 3 // bits de sel -> 2^SEL_W entradas
)(
input [(1<<SEL_W) * DATA_W - 1 : 0] in,
input [SEL_W-1:0] sel,
output [DATA_W-1:0] out
);
localparam INPUTS = 1 << SEL_W; // 2^3 = 8
wire [DATA_W-1:0] data [0:INPUTS-1];
genvar i;
generate
for (i=0; i<INPUTS; i = i + 1) begin: unpack
assign data[i] = in[i * DATA_W +: DATA_W];
end
endgenerate
assign out = data[sel];
endmodule