From b3d11de769100feaf7bf055d66dfe829d75a9a0e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jose=20Luis=20Monta=C3=B1es=20Ojados?=
 <joseluis@greenest.ai>
Date: Sun, 1 Mar 2026 03:29:11 +0100
Subject: [PATCH] add ram

---
 ram/ram.v    | 24 +++++++++++++++++++++++
 ram/ram_tb.v | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 roadmap.md   |  2 +-
 3 files changed, 79 insertions(+), 1 deletion(-)
 create mode 100644 ram/ram.v
 create mode 100644 ram/ram_tb.v

diff --git a/ram/ram.v b/ram/ram.v
new file mode 100644
index 0000000..4a4c5a7
--- /dev/null
+++ b/ram/ram.v
@@ -0,0 +1,24 @@
+/*
+    Ram Sincrona
+*/
+
+module ram #(
+    parameter DEPTH = 256, // posiciones
+    parameter W     = 16   // bits por posicion
+) (
+    input                       clk,
+    input                       wr_en,
+    input [$clog2(DEPTH)-1:0]   addr,
+    input [W-1:0]               wr_data,
+    output reg [W-1:0]          rd_data
+);
+    reg [W-1:0] mem [0:DEPTH-1];
+
+    always @(posedge clk) begin
+        if (wr_en)
+            mem[addr] <= wr_data;
+        else
+            rd_data <= mem[addr];
+    end
+
+endmodule
\ No newline at end of file
diff --git a/ram/ram_tb.v b/ram/ram_tb.v
new file mode 100644
index 0000000..99fba4e
--- /dev/null
+++ b/ram/ram_tb.v
@@ -0,0 +1,54 @@
+/*
+    Ram Sincrona testbench
+*/
+`include "ram/ram.v"
+
+module ram_tb;
+    reg clk, wr_en;
+    reg [7:0]   addr;
+    reg [15:0]  wr_data;
+    wire [15:0] rd_data;
+
+    ram ram1(
+        .clk(clk),
+        .wr_en(wr_en),
+        .addr(addr),
+        .wr_data(wr_data),
+        .rd_data(rd_data)
+    );
+
+    initial clk = 0;
+    always #5 clk = ~clk;
+
+    initial begin
+        $dumpfile("ram/ram.vcd");
+        $dumpvars(0, ram_tb);
+
+        wr_en = 0; addr = 0; wr_data = 0;
+        @(posedge clk);
+        $display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
+
+        wr_en = 1; addr = 25; wr_data = 256;
+        @(posedge clk);
+        $display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
+
+        wr_en = 0;
+        @(posedge clk);
+        $display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
+
+        @(posedge clk);
+        $display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
+
+        addr = 16;
+
+        @(posedge clk);
+        $display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
+
+        @(posedge clk);
+        $display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
+
+
+        $finish;
+    end
+    
+endmodule
\ No newline at end of file
diff --git a/roadmap.md b/roadmap.md
index 8878cc8..4987f99 100644
--- a/roadmap.md
+++ b/roadmap.md
@@ -351,7 +351,7 @@ gtkwave modulo.vcd
 - [x] Fase 2.2 — Contador
 - [x] Fase 2.3 — Shift Register
 - [x] Fase 2.4 — Register File
-- [ ] Fase 3.1 — RAM sincrona
+- [x] Fase 3.1 — RAM sincrona
 - [ ] Fase 3.2 — ROM
 - [ ] Fase 3.3 — Stack
 - [ ] Fase 4.1 — FSM Semaforo