From cec82dc58f4a4bb7eb153a984f1c302b5af9ee16 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jose=20Luis=20Monta=C3=B1es=20Ojados?=
 <joseluis@greenest.ai>
Date: Sun, 1 Mar 2026 02:58:20 +0100
Subject: [PATCH] add register_file

---
 register_file/register_file.v    | 38 ++++++++++++++++++++
 register_file/register_file_tb.v | 60 ++++++++++++++++++++++++++++++++
 roadmap.md                       |  2 +-
 3 files changed, 99 insertions(+), 1 deletion(-)
 create mode 100644 register_file/register_file.v
 create mode 100644 register_file/register_file_tb.v

diff --git a/register_file/register_file.v b/register_file/register_file.v
new file mode 100644
index 0000000..f5242b6
--- /dev/null
+++ b/register_file/register_file.v
@@ -0,0 +1,38 @@
+/*
+    Registros
+*/
+
+module register_file #(
+    parameter REGS = 16,
+    parameter W    = 16
+) (
+    input                       clk,
+    input                       rst,
+    // Puerto escritura
+    input [$clog2(REGS)-1:0]    wr_addr,
+    input [W-1:0]               wr_data,
+    input                       wr_en,
+    // Puerto lectura 1
+    input [$clog2(REGS)-1:0]    rd_addr1,
+    output [W-1:0]              rd_data1,
+    // Puerto lectura 2
+    input [$clog2(REGS)-1:0]    rd_addr2,
+    output [W-1:0]              rd_data2
+);
+    reg [W-1:0] regs [0:REGS-1];
+
+    // Lectura combinacional
+    assign rd_data1 = regs[rd_addr1];
+    assign rd_data2 = regs[rd_addr2];
+
+    // Escritura sincrona
+    integer i;
+    always @(posedge clk or posedge rst) begin
+       if (rst) begin
+        for (i = 0; i < REGS; i = i + 1)
+            regs[i] <= 0;
+       end else if (wr_en) begin
+            regs[wr_addr] <= wr_data;
+       end
+    end
+endmodule
\ No newline at end of file
diff --git a/register_file/register_file_tb.v b/register_file/register_file_tb.v
new file mode 100644
index 0000000..58f48b1
--- /dev/null
+++ b/register_file/register_file_tb.v
@@ -0,0 +1,60 @@
+/*
+    Registros
+*/
+`include "./register_file/register_file.v"
+module register_file_tb;
+    reg clk, rst, wr_en;
+    reg [3:0] wr_addr;
+    reg [15:0] wr_data;
+    reg [3:0] rd_addr1, rd_addr2;
+    wire [15:0] rd_value1, rd_value2;
+
+    register_file register(
+        .clk(clk),
+        .rst(rst),
+        .wr_addr(wr_addr),
+        .wr_data(wr_data),
+        .wr_en(wr_en),
+        .rd_addr1(rd_addr1),
+        .rd_data1(rd_value1),
+        .rd_addr2(rd_addr2),
+        .rd_data2(rd_value2)
+    );
+
+    initial clk = 0;
+    always #5 clk = ~clk;
+
+    initial begin
+        $dumpfile("register_file/register_file.vcd");
+        $dumpvars(0, register_file_tb);
+
+        rst = 1; wr_en = 0; wr_addr = 0; wr_data = 0;
+        rd_addr1 = 0; rd_addr2 = 0;
+        @(posedge clk);
+        $display("rst=%b, wr_en=%b, wr_add=%d, wr_data=%d", rst, wr_en, wr_addr, wr_data);
+        $display("rd_addr1=%d, rd_addr2=%d, rd_value1=%d, rd_value2=%d", rd_addr1, rd_addr2, rd_value1, rd_value2);
+
+        rst = 0;
+        @(posedge clk);
+        $display("rst=%b, wr_en=%b, wr_add=%d, wr_data=%d", rst, wr_en, wr_addr, wr_data);
+        $display("rd_addr1=%d, rd_addr2=%d, rd_value1=%d, rd_value2=%d", rd_addr1, rd_addr2, rd_value1, rd_value2);
+
+        wr_en = 1; wr_addr = 1; wr_data = 16'hBEEF;
+        @(posedge clk);
+        $display("rst=%b, wr_en=%b, wr_add=%d, wr_data=%d", rst, wr_en, wr_addr, wr_data);
+        $display("rd_addr1=%d, rd_addr2=%d, rd_value1=%d, rd_value2=%d", rd_addr1, rd_addr2, rd_value1, rd_value2);
+
+        wr_en = 0;
+        @(posedge clk);
+        $display("rst=%b, wr_en=%b, wr_add=%d, wr_data=%d", rst, wr_en, wr_addr, wr_data);
+        $display("rd_addr1=%d, rd_addr2=%d, rd_value1=%d, rd_value2=%d", rd_addr1, rd_addr2, rd_value1, rd_value2);
+
+        rd_addr1 = 1;
+        @(posedge clk);
+        $display("rst=%b, wr_en=%b, wr_add=%d, wr_data=%d", rst, wr_en, wr_addr, wr_data);
+        $display("rd_addr1=%d, rd_addr2=%d, rd_value1=%d, rd_value2=%d", rd_addr1, rd_addr2, rd_value1, rd_value2);
+
+        repeat(100) @(posedge clk);
+        $finish;
+    end
+endmodule
\ No newline at end of file
diff --git a/roadmap.md b/roadmap.md
index 6efa857..8878cc8 100644
--- a/roadmap.md
+++ b/roadmap.md
@@ -350,7 +350,7 @@ gtkwave modulo.vcd
 - [x] Fase 2.1 — Flip-Flop D y registro
 - [x] Fase 2.2 — Contador
 - [x] Fase 2.3 — Shift Register
-- [ ] Fase 2.4 — Register File
+- [x] Fase 2.4 — Register File
 - [ ] Fase 3.1 — RAM sincrona
 - [ ] Fase 3.2 — ROM
 - [ ] Fase 3.3 — Stack