first commit
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330
adder_nbit/adder_nbit.vcd
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330
adder_nbit/adder_nbit.vcd
Normal file
@@ -0,0 +1,330 @@
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$date
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Sat Feb 28 20:27:33 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module adder_nbit_tb $end
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$var wire 1 ! carry_out $end
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$var wire 8 " sum [7:0] $end
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$var reg 8 # a [7:0] $end
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$var reg 8 $ b [7:0] $end
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$var reg 1 % carry_in $end
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$scope module adder_8bit $end
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$var wire 8 & a [7:0] $end
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$var wire 8 ' b [7:0] $end
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$var wire 9 ( carry [8:0] $end
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$var wire 1 ) carry_in $end
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$var wire 1 ! carry_out $end
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$var wire 8 * sum [7:0] $end
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$scope begin generar_full_adder[0] $end
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$scope module full_adder $end
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$var wire 1 + a $end
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$var wire 1 , add1_carry $end
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$var wire 1 - add1_sum $end
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$var wire 1 . add2_carry $end
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$var wire 1 / b $end
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$var wire 1 0 carry_in $end
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$var wire 1 1 carry_out $end
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$var wire 1 2 sum $end
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$scope module add1 $end
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$var wire 1 + a $end
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$var wire 1 / b $end
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$var wire 1 , carry $end
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$var wire 1 - sum $end
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$upscope $end
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$scope module add2 $end
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$var wire 1 - a $end
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$var wire 1 0 b $end
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$var wire 1 . carry $end
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$var wire 1 2 sum $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope begin generar_full_adder[1] $end
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$scope module full_adder $end
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$var wire 1 3 a $end
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$var wire 1 4 add1_carry $end
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$var wire 1 5 add1_sum $end
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$var wire 1 6 add2_carry $end
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$var wire 1 7 b $end
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$var wire 1 8 carry_in $end
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$var wire 1 9 carry_out $end
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$var wire 1 : sum $end
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$scope module add1 $end
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$var wire 1 3 a $end
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$var wire 1 7 b $end
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$var wire 1 4 carry $end
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$var wire 1 5 sum $end
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$upscope $end
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$scope module add2 $end
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$var wire 1 5 a $end
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$var wire 1 8 b $end
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$var wire 1 6 carry $end
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$var wire 1 : sum $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope begin generar_full_adder[2] $end
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$scope module full_adder $end
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$var wire 1 ; a $end
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$var wire 1 < add1_carry $end
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$var wire 1 = add1_sum $end
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$var wire 1 > add2_carry $end
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$var wire 1 ? b $end
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$var wire 1 @ carry_in $end
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$var wire 1 A carry_out $end
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$var wire 1 B sum $end
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$scope module add1 $end
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$var wire 1 ; a $end
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$var wire 1 ? b $end
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$var wire 1 < carry $end
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$var wire 1 = sum $end
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$upscope $end
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$scope module add2 $end
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$var wire 1 = a $end
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$var wire 1 @ b $end
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$var wire 1 > carry $end
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$var wire 1 B sum $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope begin generar_full_adder[3] $end
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$scope module full_adder $end
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$var wire 1 C a $end
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$var wire 1 D add1_carry $end
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$var wire 1 E add1_sum $end
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$var wire 1 F add2_carry $end
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$var wire 1 G b $end
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$var wire 1 H carry_in $end
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$var wire 1 I carry_out $end
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$var wire 1 J sum $end
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$scope module add1 $end
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$var wire 1 C a $end
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$var wire 1 G b $end
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$var wire 1 D carry $end
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$var wire 1 E sum $end
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$upscope $end
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$scope module add2 $end
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$var wire 1 E a $end
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$var wire 1 H b $end
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$var wire 1 F carry $end
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$var wire 1 J sum $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope begin generar_full_adder[4] $end
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$scope module full_adder $end
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$var wire 1 K a $end
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$var wire 1 L add1_carry $end
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$var wire 1 M add1_sum $end
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$var wire 1 N add2_carry $end
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$var wire 1 O b $end
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$var wire 1 P carry_in $end
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$var wire 1 Q carry_out $end
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$var wire 1 R sum $end
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$scope module add1 $end
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$var wire 1 K a $end
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$var wire 1 O b $end
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$var wire 1 L carry $end
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$var wire 1 M sum $end
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$upscope $end
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$scope module add2 $end
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$var wire 1 M a $end
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$var wire 1 P b $end
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$var wire 1 N carry $end
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$var wire 1 R sum $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope begin generar_full_adder[5] $end
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$scope module full_adder $end
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$var wire 1 S a $end
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$var wire 1 T add1_carry $end
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$var wire 1 U add1_sum $end
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$var wire 1 V add2_carry $end
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$var wire 1 W b $end
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$var wire 1 X carry_in $end
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$var wire 1 Y carry_out $end
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$var wire 1 Z sum $end
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$scope module add1 $end
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$var wire 1 S a $end
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$var wire 1 W b $end
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$var wire 1 T carry $end
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$var wire 1 U sum $end
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$upscope $end
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$scope module add2 $end
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$var wire 1 U a $end
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$var wire 1 X b $end
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$var wire 1 V carry $end
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$var wire 1 Z sum $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope begin generar_full_adder[6] $end
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$scope module full_adder $end
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$var wire 1 [ a $end
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$var wire 1 \ add1_carry $end
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$var wire 1 ] add1_sum $end
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$var wire 1 ^ add2_carry $end
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$var wire 1 _ b $end
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$var wire 1 ` carry_in $end
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$var wire 1 a carry_out $end
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$var wire 1 b sum $end
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$scope module add1 $end
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$var wire 1 [ a $end
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$var wire 1 _ b $end
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$var wire 1 \ carry $end
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$var wire 1 ] sum $end
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$upscope $end
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$scope module add2 $end
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$var wire 1 ] a $end
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$var wire 1 ` b $end
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$var wire 1 ^ carry $end
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$var wire 1 b sum $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope begin generar_full_adder[7] $end
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$scope module full_adder $end
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$var wire 1 c a $end
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$var wire 1 d add1_carry $end
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$var wire 1 e add1_sum $end
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$var wire 1 f add2_carry $end
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$var wire 1 g b $end
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$var wire 1 h carry_in $end
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$var wire 1 i carry_out $end
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$var wire 1 j sum $end
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$scope module add1 $end
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$var wire 1 c a $end
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$var wire 1 g b $end
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$var wire 1 d carry $end
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$var wire 1 e sum $end
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$upscope $end
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$scope module add2 $end
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$var wire 1 e a $end
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$var wire 1 h b $end
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$var wire 1 f carry $end
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$var wire 1 j sum $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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0j
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0i
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0h
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0g
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0f
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0e
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0d
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0c
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0b
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0a
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0`
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0_
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0^
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0]
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0\
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0[
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0Z
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0Y
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||||
0X
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||||
0W
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0V
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0U
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||||
0T
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||||
0S
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0R
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0Q
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0P
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0O
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0N
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0M
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0L
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0K
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0J
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0I
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||||
0H
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0G
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0F
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0E
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0D
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0C
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1B
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0A
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0@
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1?
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0>
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1=
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0<
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0;
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0:
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09
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08
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07
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06
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05
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04
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03
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12
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01
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00
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1/
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0.
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1-
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0,
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0+
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b101 *
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0)
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b0 (
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b101 '
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b0 &
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0%
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b101 $
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b0 #
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b101 "
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0!
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$end
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#1
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1:
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1J
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b1111 "
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b1111 *
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15
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1E
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13
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1C
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b1010 #
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b1010 &
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#2
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1H
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0:
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0B
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1A
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b1000 (
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1J
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1Z
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1b
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b1101001 "
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b1101001 *
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05
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0=
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1<
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0E
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1U
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1]
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03
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1;
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0C
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1S
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1[
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b1100100 #
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b1100100 &
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#3
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