first commit
This commit is contained in:
Jose Luis Montañes Ojados
56
alu_basic/alu_basic.v
Normal file
56
alu_basic/alu_basic.v
Normal file
@@ -0,0 +1,56 @@
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/*
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Basic ALU 16bit
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inputs: opcode, a, b
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outputs: result, zero, carry, negative
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opcode[3:0] | Operación
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-------------------------------
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0x0 | ADD
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0x1 | SUB
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0x2 | MUL
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0x3 | DIV
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0x4 | AND
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0x5 | OR
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0x6 | NOT
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0x7 | NAND
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0x8 | NOR
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0x9 | XOR
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0xA | XNOR
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0xB | NEG
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*/
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module basic_alu (
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input [3:0] opcode,
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input [15:0] a,
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input [15:0] b,
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output reg [15:0] result,
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output zero,
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output reg carry,
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output negative
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);
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always @(*) begin
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carry = 0;
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case (opcode)
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4'h0: {carry, result} = a + b; // ADD
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4'h1: {carry, result} = a - b; // SUB
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4'h2: result = a * b; // MUL
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4'h3: result = a / b; // DIV
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4'h4: result = a & b; // AND
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4'h5: result = a | b; // OR
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4'h6: result = ~a; // NOT
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4'h7: result = ~(a & b); // NAND
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4'h8: result = ~(a | b); // NOR
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4'h9: result = a ^ b; // XOR
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4'hA: result = ~(a ^ b); // XNOR
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4'hB: result = ~a + 1; // NEG
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default: result = 0;
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endcase
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end
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assign zero = result == 0;
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assign negative = result[15];
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endmodule
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133
alu_basic/alu_basic.vcd
Normal file
133
alu_basic/alu_basic.vcd
Normal file
@@ -0,0 +1,133 @@
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$date
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Sat Feb 28 21:00:53 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module basic_alu_tb $end
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$var wire 1 ! carry $end
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$var wire 1 " negative $end
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$var wire 16 # result [15:0] $end
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$var wire 1 $ zero $end
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$var reg 16 % a [15:0] $end
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$var reg 16 & b [15:0] $end
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$var reg 4 ' opcode [3:0] $end
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$scope module alu $end
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$var wire 16 ( a [15:0] $end
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$var wire 16 ) b [15:0] $end
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$var wire 1 " negative $end
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$var wire 4 * opcode [3:0] $end
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$var wire 1 $ zero $end
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$var reg 1 + carry $end
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$var reg 16 , result [15:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b11001 ,
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0+
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b0 *
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b101 )
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b10100 (
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b0 '
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b101 &
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b10100 %
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0$
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b11001 #
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0"
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0!
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$end
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#1
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b1111 ,
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b1111 #
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b1 '
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b1 *
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#2
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1+
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1!
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b0 ,
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1$
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b0 #
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b1 &
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b1 )
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b1111111111111111 %
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b1111111111111111 (
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b0 '
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b0 *
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#3
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1"
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b1111111111110001 ,
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0$
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b1111111111110001 #
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1+
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1!
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b10100 &
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b10100 )
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b101 %
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b101 (
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b1 '
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b1 *
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#4
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0"
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b111110100 ,
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b111110100 #
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0+
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0!
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b101 &
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b101 )
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b1100100 %
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b1100100 (
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b10 '
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b10 *
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#5
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b10100 ,
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b10100 #
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b11 '
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b11 *
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#6
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b111100000000 ,
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b111100000000 #
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b111111110000 &
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b111111110000 )
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b1111111100000000 %
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b1111111100000000 (
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b100 '
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b100 *
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#7
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1"
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b1111111111110000 ,
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b1111111111110000 #
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b101 '
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b101 *
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#8
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b1111111111111111 ,
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b1111111111111111 #
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b0 &
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b0 )
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b0 %
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b0 (
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b110 '
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b110 *
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#9
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b1111000011110000 ,
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b1111000011110000 #
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b111111110000 &
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b111111110000 )
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b1111111100000000 %
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b1111111100000000 (
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b1001 '
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b1001 *
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#10
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b1111111111111111 ,
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b1111111111111111 #
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b0 &
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b0 )
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b1 %
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b1 (
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b1011 '
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b1011 *
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#11
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240
alu_basic/alu_basic.vvp
Normal file
240
alu_basic/alu_basic.vvp
Normal file
@@ -0,0 +1,240 @@
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#! /c/iverilog/bin/vvp
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:ivl_version "0.9.7 " "(v0_9_7)";
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:vpi_time_precision + 0;
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:vpi_module "system";
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:vpi_module "v2005_math";
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:vpi_module "va_math";
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S_01049710 .scope module, "basic_alu_tb" "basic_alu_tb" 2 3;
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.timescale 0 0;
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v0104CEA0_0 .var "a", 15 0;
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v0104CEF8_0 .var "b", 15 0;
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v01080FC0_0 .net "carry", 0 0, v01041578_0; 1 drivers
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v010811D0_0 .net "negative", 0 0, L_010810C8; 1 drivers
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v01081070_0 .var "opcode", 3 0;
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v01080D58_0 .net "result", 15 0, v0104CDF0_0; 1 drivers
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v01081438_0 .net "zero", 0 0, L_01081018; 1 drivers
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S_01049BD8 .scope module, "alu" "basic_alu" 2 10, 3 23, S_01049710;
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.timescale 0 0;
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v01045228_0 .net *"_s0", 16 0, L_010813E0; 1 drivers
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v01045280_0 .net *"_s3", 0 0, C4<0>; 1 drivers
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v010452D8_0 .net *"_s4", 16 0, C4<00000000000000000>; 1 drivers
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v010414C8_0 .net "a", 15 0, v0104CEA0_0; 1 drivers
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v01041520_0 .net "b", 15 0, v0104CEF8_0; 1 drivers
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v01041578_0 .var "carry", 0 0;
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v0104CD40_0 .alias "negative", 0 0, v010811D0_0;
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v0104CD98_0 .net "opcode", 3 0, v01081070_0; 1 drivers
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v0104CDF0_0 .var "result", 15 0;
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v0104CE48_0 .alias "zero", 0 0, v01081438_0;
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E_01072788 .event edge, v0104CD98_0, v010414C8_0, v01041520_0;
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L_010813E0 .concat [ 16 1 0 0], v0104CDF0_0, C4<0>;
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L_01081018 .cmp/eq 17, L_010813E0, C4<00000000000000000>;
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L_010810C8 .part v0104CDF0_0, 15, 1;
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.scope S_01049BD8;
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T_0 ;
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%wait E_01072788;
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%set/v v01041578_0, 0, 1;
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%load/v 8, v0104CD98_0, 4;
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%cmpi/u 8, 0, 4;
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%jmp/1 T_0.0, 6;
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%cmpi/u 8, 1, 4;
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%jmp/1 T_0.1, 6;
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%cmpi/u 8, 2, 4;
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%jmp/1 T_0.2, 6;
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%cmpi/u 8, 3, 4;
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%jmp/1 T_0.3, 6;
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%cmpi/u 8, 4, 4;
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%jmp/1 T_0.4, 6;
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%cmpi/u 8, 5, 4;
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%jmp/1 T_0.5, 6;
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%cmpi/u 8, 6, 4;
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%jmp/1 T_0.6, 6;
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%cmpi/u 8, 7, 4;
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%jmp/1 T_0.7, 6;
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%cmpi/u 8, 8, 4;
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%jmp/1 T_0.8, 6;
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%cmpi/u 8, 9, 4;
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%jmp/1 T_0.9, 6;
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%cmpi/u 8, 10, 4;
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%jmp/1 T_0.10, 6;
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%cmpi/u 8, 11, 4;
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%jmp/1 T_0.11, 6;
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%set/v v0104CDF0_0, 0, 16;
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%jmp T_0.13;
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T_0.0 ;
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%load/v 8, v010414C8_0, 16;
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%mov 24, 0, 1;
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%load/v 25, v01041520_0, 16;
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%mov 41, 0, 1;
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%add 8, 25, 17;
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%set/v v0104CDF0_0, 8, 16;
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%set/v v01041578_0, 24, 1;
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%jmp T_0.13;
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T_0.1 ;
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%load/v 8, v010414C8_0, 16;
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%mov 24, 0, 1;
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%load/v 25, v01041520_0, 16;
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%mov 41, 0, 1;
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%sub 8, 25, 17;
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%set/v v0104CDF0_0, 8, 16;
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%set/v v01041578_0, 24, 1;
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%jmp T_0.13;
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T_0.2 ;
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%load/v 8, v010414C8_0, 16;
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%load/v 24, v01041520_0, 16;
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%mul 8, 24, 16;
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%set/v v0104CDF0_0, 8, 16;
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%jmp T_0.13;
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T_0.3 ;
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%load/v 8, v010414C8_0, 16;
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%load/v 24, v01041520_0, 16;
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%div 8, 24, 16;
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%set/v v0104CDF0_0, 8, 16;
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%jmp T_0.13;
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T_0.4 ;
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%load/v 8, v010414C8_0, 16;
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%load/v 24, v01041520_0, 16;
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%and 8, 24, 16;
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%set/v v0104CDF0_0, 8, 16;
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%jmp T_0.13;
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T_0.5 ;
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%load/v 8, v010414C8_0, 16;
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%load/v 24, v01041520_0, 16;
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%or 8, 24, 16;
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%set/v v0104CDF0_0, 8, 16;
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%jmp T_0.13;
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T_0.6 ;
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%load/v 8, v010414C8_0, 16;
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%inv 8, 16;
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%set/v v0104CDF0_0, 8, 16;
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%jmp T_0.13;
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T_0.7 ;
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%load/v 8, v010414C8_0, 16;
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%load/v 24, v01041520_0, 16;
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%and 8, 24, 16;
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%inv 8, 16;
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%set/v v0104CDF0_0, 8, 16;
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%jmp T_0.13;
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T_0.8 ;
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%load/v 8, v010414C8_0, 16;
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%load/v 24, v01041520_0, 16;
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%or 8, 24, 16;
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%inv 8, 16;
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%set/v v0104CDF0_0, 8, 16;
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%jmp T_0.13;
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T_0.9 ;
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%load/v 8, v010414C8_0, 16;
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%load/v 24, v01041520_0, 16;
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%xor 8, 24, 16;
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%set/v v0104CDF0_0, 8, 16;
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%jmp T_0.13;
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T_0.10 ;
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%load/v 8, v010414C8_0, 16;
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%load/v 24, v01041520_0, 16;
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%xor 8, 24, 16;
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%inv 8, 16;
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%set/v v0104CDF0_0, 8, 16;
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%jmp T_0.13;
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T_0.11 ;
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%load/v 8, v010414C8_0, 16;
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%mov 24, 0, 16;
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%inv 8, 32;
|
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%addi 8, 1, 32;
|
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%set/v v0104CDF0_0, 8, 16;
|
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%jmp T_0.13;
|
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T_0.13 ;
|
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%jmp T_0;
|
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.thread T_0, $push;
|
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.scope S_01049710;
|
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T_1 ;
|
||||
%vpi_call 2 21 "$dumpfile", "./alu_basic/alu_basic.vcd";
|
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%vpi_call 2 22 "$dumpvars", 1'sb0, S_01049710;
|
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%set/v v01081070_0, 0, 4;
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%movi 8, 20, 16;
|
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%set/v v0104CEA0_0, 8, 16;
|
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%movi 8, 5, 16;
|
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%set/v v0104CEF8_0, 8, 16;
|
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%delay 1, 0;
|
||||
%vpi_call 2 26 "$display", "opcode=%d, a=%d, b=%d, result=%d, zero=%b, carry=%b, negative=%b", v01081070_0, v0104CEA0_0, v0104CEF8_0, v01080D58_0, v01081438_0, v01080FC0_0, v010811D0_0;
|
||||
%movi 8, 1, 4;
|
||||
%set/v v01081070_0, 8, 4;
|
||||
%movi 8, 20, 16;
|
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%set/v v0104CEA0_0, 8, 16;
|
||||
%movi 8, 5, 16;
|
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%set/v v0104CEF8_0, 8, 16;
|
||||
%delay 1, 0;
|
||||
%vpi_call 2 29 "$display", "opcode=%d, a=%d, b=%d, result=%d, zero=%b, carry=%b, negative=%b", v01081070_0, v0104CEA0_0, v0104CEF8_0, v01080D58_0, v01081438_0, v01080FC0_0, v010811D0_0;
|
||||
%set/v v01081070_0, 0, 4;
|
||||
%set/v v0104CEA0_0, 1, 16;
|
||||
%movi 8, 1, 16;
|
||||
%set/v v0104CEF8_0, 8, 16;
|
||||
%delay 1, 0;
|
||||
%vpi_call 2 34 "$display", "opcode=%d, a=%d, b=%d, result=%d, zero=%b, carry=%b, negative=%b", v01081070_0, v0104CEA0_0, v0104CEF8_0, v01080D58_0, v01081438_0, v01080FC0_0, v010811D0_0;
|
||||
%movi 8, 1, 4;
|
||||
%set/v v01081070_0, 8, 4;
|
||||
%movi 8, 5, 16;
|
||||
%set/v v0104CEA0_0, 8, 16;
|
||||
%movi 8, 20, 16;
|
||||
%set/v v0104CEF8_0, 8, 16;
|
||||
%delay 1, 0;
|
||||
%vpi_call 2 39 "$display", "opcode=%d, a=%d, b=%d, result=%d, zero=%b, carry=%b, negative=%b", v01081070_0, v0104CEA0_0, v0104CEF8_0, v01080D58_0, v01081438_0, v01080FC0_0, v010811D0_0;
|
||||
%movi 8, 2, 4;
|
||||
%set/v v01081070_0, 8, 4;
|
||||
%movi 8, 100, 16;
|
||||
%set/v v0104CEA0_0, 8, 16;
|
||||
%movi 8, 5, 16;
|
||||
%set/v v0104CEF8_0, 8, 16;
|
||||
%delay 1, 0;
|
||||
%vpi_call 2 44 "$display", "opcode=%d, a=%d, b=%d, result=%d, zero=%b, carry=%b, negative=%b", v01081070_0, v0104CEA0_0, v0104CEF8_0, v01080D58_0, v01081438_0, v01080FC0_0, v010811D0_0;
|
||||
%movi 8, 3, 4;
|
||||
%set/v v01081070_0, 8, 4;
|
||||
%movi 8, 100, 16;
|
||||
%set/v v0104CEA0_0, 8, 16;
|
||||
%movi 8, 5, 16;
|
||||
%set/v v0104CEF8_0, 8, 16;
|
||||
%delay 1, 0;
|
||||
%vpi_call 2 49 "$display", "opcode=%d, a=%d, b=%d, result=%d, zero=%b, carry=%b, negative=%b", v01081070_0, v0104CEA0_0, v0104CEF8_0, v01080D58_0, v01081438_0, v01080FC0_0, v010811D0_0;
|
||||
%movi 8, 4, 4;
|
||||
%set/v v01081070_0, 8, 4;
|
||||
%movi 8, 65280, 16;
|
||||
%set/v v0104CEA0_0, 8, 16;
|
||||
%movi 8, 4080, 16;
|
||||
%set/v v0104CEF8_0, 8, 16;
|
||||
%delay 1, 0;
|
||||
%vpi_call 2 54 "$display", "opcode=%h, a=%h, b=%h, result=%h, zero=%b, carry=%b, negative=%b", v01081070_0, v0104CEA0_0, v0104CEF8_0, v01080D58_0, v01081438_0, v01080FC0_0, v010811D0_0;
|
||||
%movi 8, 5, 4;
|
||||
%set/v v01081070_0, 8, 4;
|
||||
%movi 8, 65280, 16;
|
||||
%set/v v0104CEA0_0, 8, 16;
|
||||
%movi 8, 4080, 16;
|
||||
%set/v v0104CEF8_0, 8, 16;
|
||||
%delay 1, 0;
|
||||
%vpi_call 2 59 "$display", "opcode=%h, a=%h, b=%h, result=%h, zero=%b, carry=%b, negative=%b", v01081070_0, v0104CEA0_0, v0104CEF8_0, v01080D58_0, v01081438_0, v01080FC0_0, v010811D0_0;
|
||||
%movi 8, 6, 4;
|
||||
%set/v v01081070_0, 8, 4;
|
||||
%set/v v0104CEA0_0, 0, 16;
|
||||
%set/v v0104CEF8_0, 0, 16;
|
||||
%delay 1, 0;
|
||||
%vpi_call 2 64 "$display", "opcode=%d, a=%d, b=%d, result=%d, zero=%b, carry=%b, negative=%b", v01081070_0, v0104CEA0_0, v0104CEF8_0, v01080D58_0, v01081438_0, v01080FC0_0, v010811D0_0;
|
||||
%movi 8, 9, 4;
|
||||
%set/v v01081070_0, 8, 4;
|
||||
%movi 8, 65280, 16;
|
||||
%set/v v0104CEA0_0, 8, 16;
|
||||
%movi 8, 4080, 16;
|
||||
%set/v v0104CEF8_0, 8, 16;
|
||||
%delay 1, 0;
|
||||
%vpi_call 2 69 "$display", "opcode=%h, a=%h, b=%h, result=%h, zero=%b, carry=%b, negative=%b", v01081070_0, v0104CEA0_0, v0104CEF8_0, v01080D58_0, v01081438_0, v01080FC0_0, v010811D0_0;
|
||||
%movi 8, 11, 4;
|
||||
%set/v v01081070_0, 8, 4;
|
||||
%movi 8, 1, 16;
|
||||
%set/v v0104CEA0_0, 8, 16;
|
||||
%set/v v0104CEF8_0, 0, 16;
|
||||
%delay 1, 0;
|
||||
%vpi_call 2 74 "$display", "opcode=%d, a=%d, b=%d, result=%d, zero=%b, carry=%b, negative=%b", v01081070_0, v0104CEA0_0, v0104CEF8_0, v01080D58_0, v01081438_0, v01080FC0_0, v010811D0_0;
|
||||
%end;
|
||||
.thread T_1;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
".\alu_basic\alu_basic_tb.v";
|
||||
"././alu_basic/alu_basic.v";
|
||||
77
alu_basic/alu_basic_tb.v
Normal file
77
alu_basic/alu_basic_tb.v
Normal file
@@ -0,0 +1,77 @@
|
||||
`include "./alu_basic/alu_basic.v"
|
||||
|
||||
module basic_alu_tb;
|
||||
reg [15:0] a, b;
|
||||
reg [3:0] opcode;
|
||||
|
||||
wire [15:0] result;
|
||||
wire zero, carry, negative;
|
||||
|
||||
basic_alu alu(
|
||||
.opcode(opcode),
|
||||
.a(a),
|
||||
.b(b),
|
||||
.result(result),
|
||||
.zero(zero),
|
||||
.carry(carry),
|
||||
.negative(negative)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("./alu_basic/alu_basic.vcd");
|
||||
$dumpvars(0, basic_alu_tb);
|
||||
|
||||
opcode = 4'h0; a = 20; b = 5;
|
||||
#1
|
||||
$display("opcode=%d, a=%d, b=%d, result=%d, zero=%b, carry=%b, negative=%b", opcode, a, b, result, zero, carry, negative);
|
||||
opcode = 4'h1; a = 20; b = 5;
|
||||
#1
|
||||
$display("opcode=%d, a=%d, b=%d, result=%d, zero=%b, carry=%b, negative=%b", opcode, a, b, result, zero, carry, negative);
|
||||
|
||||
// ADD con overflow: 65535 + 1 = 0, carry=1, zero=1
|
||||
opcode = 4'h0; a = 16'hFFFF; b = 1;
|
||||
#1
|
||||
$display("opcode=%d, a=%d, b=%d, result=%d, zero=%b, carry=%b, negative=%b", opcode, a, b, result, zero, carry, negative);
|
||||
|
||||
// SUB con negativo: 5 - 20, negative=1
|
||||
opcode = 4'h1; a = 5; b = 20;
|
||||
#1
|
||||
$display("opcode=%d, a=%d, b=%d, result=%d, zero=%b, carry=%b, negative=%b", opcode, a, b, result, zero, carry, negative);
|
||||
|
||||
// MUL: 100 * 5 = 500
|
||||
opcode = 4'h2; a = 100; b = 5;
|
||||
#1
|
||||
$display("opcode=%d, a=%d, b=%d, result=%d, zero=%b, carry=%b, negative=%b", opcode, a, b, result, zero, carry, negative);
|
||||
|
||||
// DIV: 100 / 5 = 20
|
||||
opcode = 4'h3; a = 100; b = 5;
|
||||
#1
|
||||
$display("opcode=%d, a=%d, b=%d, result=%d, zero=%b, carry=%b, negative=%b", opcode, a, b, result, zero, carry, negative);
|
||||
|
||||
// AND: 0xFF00 & 0x0FF0 = 0x0F00
|
||||
opcode = 4'h4; a = 16'hFF00; b = 16'h0FF0;
|
||||
#1
|
||||
$display("opcode=%h, a=%h, b=%h, result=%h, zero=%b, carry=%b, negative=%b", opcode, a, b, result, zero, carry, negative);
|
||||
|
||||
// OR: 0xFF00 | 0x0FF0 = 0xFFF0
|
||||
opcode = 4'h5; a = 16'hFF00; b = 16'h0FF0;
|
||||
#1
|
||||
$display("opcode=%h, a=%h, b=%h, result=%h, zero=%b, carry=%b, negative=%b", opcode, a, b, result, zero, carry, negative);
|
||||
|
||||
// NOT: ~0 = 65535
|
||||
opcode = 4'h6; a = 0; b = 0;
|
||||
#1
|
||||
$display("opcode=%d, a=%d, b=%d, result=%d, zero=%b, carry=%b, negative=%b", opcode, a, b, result, zero, carry, negative);
|
||||
|
||||
// XOR: 0xFF00 ^ 0x0FF0 = 0xF0F0
|
||||
opcode = 4'h9; a = 16'hFF00; b = 16'h0FF0;
|
||||
#1
|
||||
$display("opcode=%h, a=%h, b=%h, result=%h, zero=%b, carry=%b, negative=%b", opcode, a, b, result, zero, carry, negative);
|
||||
|
||||
// NEG: -1 en complemento a 2 = 65535
|
||||
opcode = 4'hB; a = 1; b = 0;
|
||||
#1
|
||||
$display("opcode=%d, a=%d, b=%d, result=%d, zero=%b, carry=%b, negative=%b", opcode, a, b, result, zero, carry, negative);
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user