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Jose Luis Montañes Ojados
2026-02-28 21:59:55 +01:00
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/*
Basic ALU 16bit
inputs: opcode, a, b
outputs: result, zero, carry, negative
opcode[3:0] | Operación
-------------------------------
0x0 | ADD
0x1 | SUB
0x2 | MUL
0x3 | DIV
0x4 | AND
0x5 | OR
0x6 | NOT
0x7 | NAND
0x8 | NOR
0x9 | XOR
0xA | XNOR
0xB | NEG
*/
module basic_alu (
input [3:0] opcode,
input [15:0] a,
input [15:0] b,
output reg [15:0] result,
output zero,
output reg carry,
output negative
);
always @(*) begin
carry = 0;
case (opcode)
4'h0: {carry, result} = a + b; // ADD
4'h1: {carry, result} = a - b; // SUB
4'h2: result = a * b; // MUL
4'h3: result = a / b; // DIV
4'h4: result = a & b; // AND
4'h5: result = a | b; // OR
4'h6: result = ~a; // NOT
4'h7: result = ~(a & b); // NAND
4'h8: result = ~(a | b); // NOR
4'h9: result = a ^ b; // XOR
4'hA: result = ~(a ^ b); // XNOR
4'hB: result = ~a + 1; // NEG
default: result = 0;
endcase
end
assign zero = result == 0;
assign negative = result[15];
endmodule