first commit

alu_basic/alu_basic.vcd

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+$date
+	Sat Feb 28 21:00:53 2026
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module basic_alu_tb $end
+$var wire 1 ! carry $end
+$var wire 1 " negative $end
+$var wire 16 # result [15:0] $end
+$var wire 1 $ zero $end
+$var reg 16 % a [15:0] $end
+$var reg 16 & b [15:0] $end
+$var reg 4 ' opcode [3:0] $end
+$scope module alu $end
+$var wire 16 ( a [15:0] $end
+$var wire 16 ) b [15:0] $end
+$var wire 1 " negative $end
+$var wire 4 * opcode [3:0] $end
+$var wire 1 $ zero $end
+$var reg 1 + carry $end
+$var reg 16 , result [15:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b11001 ,
+0+
+b0 *
+b101 )
+b10100 (
+b0 '
+b101 &
+b10100 %
+0$
+b11001 #
+0"
+0!
+$end
+#1
+b1111 ,
+b1111 #
+b1 '
+b1 *
+#2
+1+
+1!
+b0 ,
+1$
+b0 #
+b1 &
+b1 )
+b1111111111111111 %
+b1111111111111111 (
+b0 '
+b0 *
+#3
+1"
+b1111111111110001 ,
+0$
+b1111111111110001 #
+1+
+1!
+b10100 &
+b10100 )
+b101 %
+b101 (
+b1 '
+b1 *
+#4
+0"
+b111110100 ,
+b111110100 #
+0+
+0!
+b101 &
+b101 )
+b1100100 %
+b1100100 (
+b10 '
+b10 *
+#5
+b10100 ,
+b10100 #
+b11 '
+b11 *
+#6
+b111100000000 ,
+b111100000000 #
+b111111110000 &
+b111111110000 )
+b1111111100000000 %
+b1111111100000000 (
+b100 '
+b100 *
+#7
+1"
+b1111111111110000 ,
+b1111111111110000 #
+b101 '
+b101 *
+#8
+b1111111111111111 ,
+b1111111111111111 #
+b0 &
+b0 )
+b0 %
+b0 (
+b110 '
+b110 *
+#9
+b1111000011110000 ,
+b1111000011110000 #
+b111111110000 &
+b111111110000 )
+b1111111100000000 %
+b1111111100000000 (
+b1001 '
+b1001 *
+#10
+b1111111111111111 ,
+b1111111111111111 #
+b0 &
+b0 )
+b1 %
+b1 (
+b1011 '
+b1011 *
+#11