first commit
This commit is contained in:
Jose Luis Montañes Ojados
45
full_adder/full_adder.v
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45
full_adder/full_adder.v
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/*
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Full Adder Declaration
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A B Cin | Sum Cout
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0 0 0 | 0 0
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0 0 1 | 1 0
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0 1 0 | 1 0
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0 1 1 | 0 1
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1 0 0 | 1 0
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1 0 1 | 0 1
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1 1 0 | 0 1
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1 1 1 | 1 1
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*/
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`include "./half_adder/half_adder.v"
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module full_adder_structural (carry_in, a, b, sum, carry_out);
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input carry_in, a, b;
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output sum, carry_out;
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wire add1_sum, add1_carry;
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wire add2_carry;
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half_adder add1(a, b, add1_sum, add1_carry);
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half_adder add2(add1_sum, carry_in, sum, add2_carry);
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or final_or(carry_out, add1_carry, add2_carry);
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endmodule
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module full_adder_dataflow (carry_in, a, b, sum, carry_out);
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input carry_in, a, b;
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output sum, carry_out;
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assign sum = a ^ b ^ carry_in;
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assign carry_out = (a & b) | (carry_in & (a ^ b));
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endmodule
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module full_adder_behavioral (carry_in, a, b, sum, carry_out);
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input carry_in, a, b;
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output reg sum, carry_out;
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always @(*) begin
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sum = a ^ b ^ carry_in;
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carry_out = (a & b) | (carry_in & (a ^ b));
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end
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endmodule
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69
full_adder/full_adder.vcd
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69
full_adder/full_adder.vcd
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$date
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Sat Feb 28 20:25:22 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module full_adder_tb $end
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$var wire 1 ! carry_out $end
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$var wire 1 " sum $end
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$var reg 1 # a $end
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$var reg 1 $ b $end
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$var reg 1 % carry_in $end
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$scope module full_adder $end
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$var wire 1 & a $end
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$var wire 1 ' b $end
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$var wire 1 ( carry_in $end
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$var reg 1 ) carry_out $end
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$var reg 1 * sum $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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0*
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0)
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0(
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0'
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0&
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0%
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0$
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0#
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0"
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0!
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$end
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#1
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1*
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1"
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1%
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1(
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#2
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0*
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0"
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0%
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0(
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#3
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1*
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1"
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1#
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1&
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#4
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1)
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1!
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0*
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0"
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1%
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1(
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#5
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0%
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0(
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1$
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1'
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#6
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1*
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1"
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1%
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1(
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154
full_adder/full_adder.vvp
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154
full_adder/full_adder.vvp
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#! /c/iverilog/bin/vvp
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:ivl_version "0.9.7 " "(v0_9_7)";
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:vpi_time_precision + 0;
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:vpi_module "system";
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:vpi_module "v2005_math";
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:vpi_module "va_math";
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S_01022BC0 .scope module, "full_adder_dataflow" "full_adder_dataflow" 2 29;
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.timescale 0 0;
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L_000ED8B8 .functor XOR 1, C4<z>, C4<z>, C4<0>, C4<0>;
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L_000ED8F0 .functor XOR 1, L_000ED8B8, C4<z>, C4<0>, C4<0>;
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L_0105BC40 .functor AND 1, C4<z>, C4<z>, C4<1>, C4<1>;
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L_0105BE00 .functor XOR 1, C4<z>, C4<z>, C4<0>, C4<0>;
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L_0105BFC0 .functor AND 1, C4<z>, L_0105BE00, C4<1>, C4<1>;
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L_0105BC78 .functor OR 1, L_0105BC40, L_0105BFC0, C4<0>, C4<0>;
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v000ED828_0 .net *"_s0", 0 0, L_000ED8B8; 1 drivers
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v01030E00_0 .net *"_s4", 0 0, L_0105BC40; 1 drivers
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v01031278_0 .net *"_s6", 0 0, L_0105BE00; 1 drivers
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v01030FB8_0 .net *"_s8", 0 0, L_0105BFC0; 1 drivers
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v01030F60_0 .net "a", 0 0, C4<z>; 0 drivers
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v01030CF8_0 .net "b", 0 0, C4<z>; 0 drivers
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v01030E58_0 .net "carry_in", 0 0, C4<z>; 0 drivers
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v010311C8_0 .net "carry_out", 0 0, L_0105BC78; 1 drivers
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v01030D50_0 .net "sum", 0 0, L_000ED8F0; 1 drivers
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S_01023220 .scope module, "full_adder_structural" "full_adder_structural" 2 16;
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.timescale 0 0;
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L_0105C2F0 .functor OR 1, L_0105BD90, L_0105C750, C4<0>, C4<0>;
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v01031068_0 .net "a", 0 0, C4<z>; 0 drivers
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v01031430_0 .net "add1_carry", 0 0, L_0105BD90; 1 drivers
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v01031118_0 .net "add1_sum", 0 0, L_0105BCB0; 1 drivers
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v01031170_0 .net "add2_carry", 0 0, L_0105C750; 1 drivers
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v01030DA8_0 .net "b", 0 0, C4<z>; 0 drivers
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v01030F08_0 .net "carry_in", 0 0, C4<z>; 0 drivers
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v0105B3D0_0 .net "carry_out", 0 0, L_0105C2F0; 1 drivers
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v0105B270_0 .net "sum", 0 0, L_0105BF88; 1 drivers
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S_01022AB0 .scope module, "add1" "half_adder" 2 23, 3 5, S_01023220;
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.timescale 0 0;
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L_0105BCB0 .functor XOR 1, C4<z>, C4<z>, C4<0>, C4<0>;
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L_0105BD90 .functor AND 1, C4<z>, C4<z>, C4<1>, C4<1>;
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v010312D0_0 .alias "a", 0 0, v01031068_0;
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v01030EB0_0 .alias "b", 0 0, v01030DA8_0;
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v01031328_0 .alias "carry", 0 0, v01031430_0;
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v01031380_0 .alias "sum", 0 0, v01031118_0;
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S_01023660 .scope module, "add2" "half_adder" 2 24, 3 5, S_01023220;
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.timescale 0 0;
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L_0105BF88 .functor XOR 1, L_0105BCB0, C4<z>, C4<0>, C4<0>;
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L_0105C750 .functor AND 1, L_0105BCB0, C4<z>, C4<1>, C4<1>;
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v01031010_0 .alias "a", 0 0, v01031118_0;
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v010313D8_0 .alias "b", 0 0, v01030F08_0;
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v01031220_0 .alias "carry", 0 0, v01031170_0;
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v010310C0_0 .alias "sum", 0 0, v0105B270_0;
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S_010234C8 .scope module, "full_adder_tb" "full_adder_tb" 4 6;
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.timescale 0 0;
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v0105B588_0 .var "a", 0 0;
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v0105B2C8_0 .var "b", 0 0;
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v0105B320_0 .var "carry_in", 0 0;
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v0105B1C0_0 .net "carry_out", 0 0, v0105B110_0; 1 drivers
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v0105B638_0 .net "sum", 0 0, v0105ADA0_0; 1 drivers
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S_010229A0 .scope module, "full_adder" "full_adder_behavioral" 4 10, 2 37, S_010234C8;
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.timescale 0 0;
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v0105B218_0 .net "a", 0 0, v0105B588_0; 1 drivers
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v0105B5E0_0 .net "b", 0 0, v0105B2C8_0; 1 drivers
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v0105B008_0 .net "carry_in", 0 0, v0105B320_0; 1 drivers
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v0105B110_0 .var "carry_out", 0 0;
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v0105ADA0_0 .var "sum", 0 0;
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E_01023A48 .event edge, v0105B218_0, v0105B5E0_0, v0105B008_0;
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S_01022EF0 .scope module, "half_adder_behavioral" "half_adder_behavioral" 3 21;
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.timescale 0 0;
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v0105AC98_0 .net "a", 0 0, C4<z>; 0 drivers
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v0105B060_0 .net "b", 0 0, C4<z>; 0 drivers
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v0105ACF0_0 .var "carry", 0 0;
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v0105B428_0 .var "sum", 0 0;
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E_01023B28 .event edge, v0105B060_0, v0105AC98_0;
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S_010232A8 .scope module, "half_adder_dataflow" "half_adder_dataflow" 3 13;
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.timescale 0 0;
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L_0105C1A0 .functor XOR 1, C4<z>, C4<z>, C4<0>, C4<0>;
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L_0105C1D8 .functor AND 1, C4<z>, C4<z>, C4<1>, C4<1>;
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v0105B530_0 .net "a", 0 0, C4<z>; 0 drivers
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v0105B378_0 .net "b", 0 0, C4<z>; 0 drivers
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v0105AC40_0 .net "carry", 0 0, L_0105C1D8; 1 drivers
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v0105ADF8_0 .net "sum", 0 0, L_0105C1A0; 1 drivers
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.scope S_010229A0;
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T_0 ;
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%wait E_01023A48;
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%load/v 8, v0105B218_0, 1;
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%load/v 9, v0105B5E0_0, 1;
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%xor 8, 9, 1;
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%load/v 9, v0105B008_0, 1;
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%xor 8, 9, 1;
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%set/v v0105ADA0_0, 8, 1;
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%load/v 8, v0105B218_0, 1;
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%load/v 9, v0105B5E0_0, 1;
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%and 8, 9, 1;
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%load/v 9, v0105B008_0, 1;
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%load/v 10, v0105B218_0, 1;
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%load/v 11, v0105B5E0_0, 1;
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%xor 10, 11, 1;
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%and 9, 10, 1;
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%or 8, 9, 1;
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%set/v v0105B110_0, 8, 1;
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%jmp T_0;
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.thread T_0, $push;
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.scope S_010234C8;
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T_1 ;
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%vpi_call 4 19 "$dumpfile", "./full_adder/full_adder.vcd";
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%vpi_call 4 20 "$dumpvars", 1'sb0, S_010234C8;
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%set/v v0105B588_0, 0, 1;
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%set/v v0105B2C8_0, 0, 1;
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%set/v v0105B320_0, 0, 1;
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%delay 1, 0;
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%set/v v0105B588_0, 0, 1;
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%set/v v0105B2C8_0, 0, 1;
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%set/v v0105B320_0, 1, 1;
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%delay 1, 0;
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%set/v v0105B588_0, 0, 1;
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%set/v v0105B2C8_0, 0, 1;
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%set/v v0105B320_0, 0, 1;
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%delay 1, 0;
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%set/v v0105B588_0, 1, 1;
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%set/v v0105B2C8_0, 0, 1;
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%set/v v0105B320_0, 0, 1;
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%delay 1, 0;
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%set/v v0105B588_0, 1, 1;
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%set/v v0105B2C8_0, 0, 1;
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%set/v v0105B320_0, 1, 1;
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%delay 1, 0;
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%set/v v0105B588_0, 1, 1;
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%set/v v0105B2C8_0, 1, 1;
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%set/v v0105B320_0, 0, 1;
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%delay 1, 0;
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%set/v v0105B588_0, 1, 1;
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%set/v v0105B2C8_0, 1, 1;
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%set/v v0105B320_0, 1, 1;
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%end;
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.thread T_1;
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.scope S_01022EF0;
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T_2 ;
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%wait E_01023B28;
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%load/v 8, v0105AC98_0, 1;
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%load/v 9, v0105B060_0, 1;
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%xor 8, 9, 1;
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%set/v v0105B428_0, 8, 1;
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%load/v 8, v0105AC98_0, 1;
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%load/v 9, v0105B060_0, 1;
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%and 8, 9, 1;
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%set/v v0105ACF0_0, 8, 1;
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%jmp T_2;
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.thread T_2, $push;
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# The file index is used to find the file name in the following table.
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:file_names 5;
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"N/A";
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"<interactive>";
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"././full_adder/full_adder.v";
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"././half_adder/half_adder.v";
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".\full_adder\full_adder_tb.v";
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36
full_adder/full_adder_tb.v
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36
full_adder/full_adder_tb.v
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@@ -0,0 +1,36 @@
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/*
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Full Adder testbench
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*/
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`include "./full_adder/full_adder.v"
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module full_adder_tb;
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reg a, b, carry_in;
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wire sum, carry_out;
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full_adder_behavioral full_adder(
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.carry_in(carry_in),
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.a(a),
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.b(b),
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.sum(sum),
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.carry_out(carry_out)
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);
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initial begin
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$dumpfile("./full_adder/full_adder.vcd");
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$dumpvars(0, full_adder_tb);
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a = 0; b = 0; carry_in = 0;
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#1
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a = 0; b = 0; carry_in = 1;
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#1
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a = 0; b = 0; carry_in = 0;
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#1
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a = 1; b = 0; carry_in = 0;
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#1
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a = 1; b = 0; carry_in = 1;
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#1
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a = 1; b = 1; carry_in = 0;
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#1
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a = 1; b = 1; carry_in = 1;
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end
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endmodule
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