first commit

full_adder/full_adder.vcd

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+$date
+	Sat Feb 28 20:25:22 2026
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module full_adder_tb $end
+$var wire 1 ! carry_out $end
+$var wire 1 " sum $end
+$var reg 1 # a $end
+$var reg 1 $ b $end
+$var reg 1 % carry_in $end
+$scope module full_adder $end
+$var wire 1 & a $end
+$var wire 1 ' b $end
+$var wire 1 ( carry_in $end
+$var reg 1 ) carry_out $end
+$var reg 1 * sum $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0*
+0)
+0(
+0'
+0&
+0%
+0$
+0#
+0"
+0!
+$end
+#1
+1*
+1"
+1%
+1(
+#2
+0*
+0"
+0%
+0(
+#3
+1*
+1"
+1#
+1&
+#4
+1)
+1!
+0*
+0"
+1%
+1(
+#5
+0%
+0(
+1$
+1'
+#6
+1*
+1"
+1%
+1(