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Jose Luis Montañes Ojados
2026-02-28 21:59:55 +01:00
commit d094ff3148
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30
half_adder/half_adder.v Normal file
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/*
Half Adder Declaration
*/
module half_adder (a,b,sum,carry);
input a,b;
output sum, carry;
xor x1(sum, a, b);
and a1(carry, a, b);
endmodule
module half_adder_dataflow (a, b, sum, carry);
input a, b;
output sum, carry;
assign sum = a ^ b;
assign carry = a & b;
endmodule
module half_adder_behavioral (a, b, sum, carry);
input a, b;
output reg sum, carry;
always @(a or b) begin
sum = a ^ b;
carry = a & b;
end
endmodule

51
half_adder/half_adder.vcd Normal file
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$date
Sat Feb 28 20:27:18 2026
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module half_adder_tb $end
$var wire 1 ! carry $end
$var wire 1 " sum $end
$var reg 1 # a $end
$var reg 1 $ b $end
$scope module add1 $end
$var wire 1 % a $end
$var wire 1 & b $end
$var wire 1 ! carry $end
$var wire 1 " sum $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0&
0%
0$
0#
0"
0!
$end
#1
1"
1$
1&
#2
0$
0&
1#
1%
#3
0"
1!
1$
1&
#4
0!
0$
0&
0#
0%

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half_adder/half_adder.vvp Normal file
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#! /c/iverilog/bin/vvp
:ivl_version "0.9.7 " "(v0_9_7)";
:vpi_time_precision + 0;
:vpi_module "system";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_00119918 .scope module, "half_adder_behavioral" "half_adder_behavioral" 2 21;
.timescale 0 0;
v0011E700_0 .net "a", 0 0, C4<z>; 0 drivers
v0011CF80_0 .net "b", 0 0, C4<z>; 0 drivers
v0011E758_0 .var "carry", 0 0;
v0011E7B0_0 .var "sum", 0 0;
E_0011A260 .event edge, v0011CF80_0, v0011E700_0;
S_001191A8 .scope module, "half_adder_dataflow" "half_adder_dataflow" 2 13;
.timescale 0 0;
L_001115D0 .functor XOR 1, C4<z>, C4<z>, C4<0>, C4<0>;
L_0011D930 .functor AND 1, C4<z>, C4<z>, C4<1>, C4<1>;
v0011D828_0 .net "a", 0 0, C4<z>; 0 drivers
v0011D880_0 .net "b", 0 0, C4<z>; 0 drivers
v0011D8D8_0 .net "carry", 0 0, L_0011D930; 1 drivers
v001114C8_0 .net "sum", 0 0, L_001115D0; 1 drivers
S_001199A0 .scope module, "half_adder_tb" "half_adder_tb" 3 6;
.timescale 0 0;
v01030A60_0 .var "a", 0 0;
v01030A08_0 .var "b", 0 0;
v01030900_0 .net "carry", 0 0, L_01031290; 1 drivers
v01030E80_0 .net "sum", 0 0, L_0011D490; 1 drivers
S_001194D8 .scope module, "add1" "half_adder" 3 10, 2 5, S_001199A0;
.timescale 0 0;
L_0011D490 .functor XOR 1, v01030A60_0, v01030A08_0, C4<0>, C4<0>;
L_01031290 .functor AND 1, v01030A60_0, v01030A08_0, C4<1>, C4<1>;
v00111520_0 .net "a", 0 0, v01030A60_0; 1 drivers
v00111578_0 .net "b", 0 0, v01030A08_0; 1 drivers
v0011D400_0 .alias "carry", 0 0, v01030900_0;
v01031038_0 .alias "sum", 0 0, v01030E80_0;
.scope S_00119918;
T_0 ;
%wait E_0011A260;
%load/v 8, v0011E700_0, 1;
%load/v 9, v0011CF80_0, 1;
%xor 8, 9, 1;
%set/v v0011E7B0_0, 8, 1;
%load/v 8, v0011E700_0, 1;
%load/v 9, v0011CF80_0, 1;
%and 8, 9, 1;
%set/v v0011E758_0, 8, 1;
%jmp T_0;
.thread T_0, $push;
.scope S_001199A0;
T_1 ;
%vpi_call 3 13 "$dumpfile", "./half_adder/half_adder.vcd";
%vpi_call 3 14 "$dumpvars", 1'sb0, S_001199A0;
%set/v v01030A60_0, 0, 1;
%set/v v01030A08_0, 0, 1;
%delay 1, 0;
%set/v v01030A60_0, 0, 1;
%set/v v01030A08_0, 1, 1;
%delay 1, 0;
%set/v v01030A60_0, 1, 1;
%set/v v01030A08_0, 0, 1;
%delay 1, 0;
%set/v v01030A60_0, 1, 1;
%set/v v01030A08_0, 1, 1;
%delay 1, 0;
%set/v v01030A60_0, 0, 1;
%set/v v01030A08_0, 0, 1;
%end;
.thread T_1;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"././half_adder/half_adder.v";
".\half_adder\half_adder_tb.v";

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half_adder/half_adder_tb.v Normal file
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/*
Testbench for half_adder
*/
`include "./half_adder/half_adder.v"
module half_adder_tb;
reg a, b;
wire sum, carry;
half_adder add1(a, b, sum, carry);
initial begin
$dumpfile("./half_adder/half_adder.vcd");
$dumpvars(0, half_adder_tb);
a = 0; b = 0;
#1
a = 0; b = 1;
#1
a = 1; b = 0;
#1
a = 1; b = 1;
#1
a = 0; b = 0;
end
endmodule

46
half_adder/half_adder_tb.vvp Normal file
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#! /c/iverilog/bin/vvp
:ivl_version "0.9.7 " "(v0_9_7)";
:vpi_time_precision + 0;
:vpi_module "system";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0122D488 .scope module, "half_adder_tb" "half_adder_tb" 2 6;
.timescale 0 0;
v01225348_0 .var "a", 0 0;
v012253A0_0 .var "b", 0 0;
v012253F8_0 .net "carry", 0 0, L_0122C4C0; 1 drivers
v01225450_0 .net "sum", 0 0, L_0122D510; 1 drivers
S_01221390 .scope module, "add1" "half_adder" 2 10, 3 5, S_0122D488;
.timescale 0 0;
L_0122D510 .functor XOR 1, v01225348_0, v012253A0_0, C4<0>, C4<0>;
L_0122C4C0 .functor AND 1, v01225348_0, v012253A0_0, C4<1>, C4<1>;
v01221418_0 .net "a", 0 0, v01225348_0; 1 drivers
v01226F88_0 .net "b", 0 0, v012253A0_0; 1 drivers
v01221470_0 .alias "carry", 0 0, v012253F8_0;
v012252F0_0 .alias "sum", 0 0, v01225450_0;
.scope S_0122D488;
T_0 ;
%vpi_call 2 13 "$dumpfile", "half_adder.vcd";
%vpi_call 2 14 "$dumpvars", 1'sb0, S_0122D488;
%set/v v01225348_0, 0, 1;
%set/v v012253A0_0, 0, 1;
%delay 1, 0;
%set/v v01225348_0, 0, 1;
%set/v v012253A0_0, 1, 1;
%delay 1, 0;
%set/v v01225348_0, 1, 1;
%set/v v012253A0_0, 0, 1;
%delay 1, 0;
%set/v v01225348_0, 1, 1;
%set/v v012253A0_0, 1, 1;
%delay 1, 0;
%set/v v01225348_0, 0, 1;
%set/v v012253A0_0, 0, 1;
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
".\half_adder_tb.v";
"./half_adder.v";

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half_adder/readme.md Normal file
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1. Compilar el testbench
`
iverilog -o .\half_adder_tb.vvp .\half_adder_tb.v
`
2. Ejecutar simulacion del testbench
`
vvp .\half_adder_tb.vvp
`
3. Visualizar ondas
`
gtkwave .\half_adder.vcd
`