first commit

half_adder/half_adder.vcd

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+$date
+	Sat Feb 28 20:27:18 2026
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module half_adder_tb $end
+$var wire 1 ! carry $end
+$var wire 1 " sum $end
+$var reg 1 # a $end
+$var reg 1 $ b $end
+$scope module add1 $end
+$var wire 1 % a $end
+$var wire 1 & b $end
+$var wire 1 ! carry $end
+$var wire 1 " sum $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0&
+0%
+0$
+0#
+0"
+0!
+$end
+#1
+1"
+1$
+1&
+#2
+0$
+0&
+1#
+1%
+#3
+0"
+1!
+1$
+1&
+#4
+0!
+0$
+0&
+0#
+0%