update roadmap

decoder_encoder/decoder_encoder.v

@@ -0,0 +1,30 @@
+/*
+    Decoder / Encoder
+*/
+
+module decoder_3bit (
+    input [2:0] in,
+    output [7:0] out
+);
+    assign out = 1 << in;
+endmodule
+
+module encoder_3bit(
+    input [7:0] in,
+    output reg [2:0] out
+);
+    always @(*) begin
+        out = 0;
+
+        casez(in) 
+            8'b1???????: out = 3'd7;
+            8'b01??????: out = 3'd6;
+            8'b001?????: out = 3'd5;
+            8'b0001????: out = 3'd4;
+            8'b00001???: out = 3'd3;
+            8'b000001??: out = 3'd2;
+            8'b0000001?: out = 3'd1;
+            8'b00000001: out = 3'd0;
+        endcase
+    end
+endmodule

decoder_encoder/decoder_encoder_tb.v

@@ -0,0 +1,38 @@
+`include "./decoder_encoder/decoder_encoder.v"
+
+module decoder_3bit_tb;
+    reg [2:0] in;
+    wire [7:0] out;
+    wire [2:0] encoded;
+
+    decoder_3bit dec(
+        .in(in),
+        .out(out)
+    ); 
+
+    encoder_3bit enc(
+        .in(out),
+        .out(encoded)
+    );
+
+    initial begin
+        $dumpfile("./decoder_encoder/decoder_encoder.vcd");
+        $dumpvars(0, decoder_3bit_tb);
+
+        in = 3'b000;
+        #1
+        $display("in=%d, out=%b, enc=%d", in, out, encoded);
+        in = 3'b001;
+        #1
+        $display("in=%d, out=%b, enc=%d", in, out, encoded);
+        in = 3'b010;
+        #1
+        $display("in=%d, out=%b, enc=%d", in, out, encoded);
+        in = 3'b100;
+        #1
+        $display("in=%d, out=%b, enc=%d", in, out, encoded);
+        in = 3'b111;
+        #1
+        $display("in=%d, out=%b, enc=%d", in, out, encoded);
+    end
+endmodule

mux_demux/mux_demux.v

@@ -32,3 +32,94 @@ module demux_1n2 #(parameter N = 8) (
     assign a = sel ? 0 : in;
     assign b = sel ? in : 0;
 endmodule
+
+module mux_4n1 #(parameter N = 8) (
+    input [N-1:0] a,
+    input [N-1:0] b,
+    input [N-1:0] c,
+    input [N-1:0] d,
+    input [1:0] sel,
+    output reg [N-1:0] out
+);
+
+    always @(*) begin
+        case (sel)
+            2'b00: out = a;
+            2'b01: out = b;
+            2'b10: out = c;
+            2'b11: out = d;
+            default: out = a;
+        endcase
+    end
+endmodule
+
+module demux_1n4 #(parameter N = 8) (
+    input [N-1:0] in,
+    input [1:0] sel,
+    output reg [N-1:0] a,
+    output reg [N-1:0] b,
+    output reg [N-1:0] c,
+    output reg [N-1:0] d
+);
+    always @(*) begin
+        a = 0; b = 0; c = 0; d = 0;
+
+        case (sel)
+            2'b00: a = in;
+            2'b01: b = in;
+            2'b10: c = in;
+            2'b11: d = in;
+            default: a = in;
+        endcase
+    end
+endmodule
+
+module mux_8n1 #(parameter N = 8) (
+    input [N-1:0] a,
+    input [N-1:0] b,
+    input [N-1:0] c,
+    input [N-1:0] d,
+    input [N-1:0] e,
+    input [N-1:0] f,
+    input [N-1:0] g,
+    input [N-1:0] h,
+    input [2:0] sel,
+    output reg [N-1:0] out
+);
+
+    always @(*) begin
+        case (sel)
+            3'b000: out = a;
+            3'b001: out = b;
+            3'b010: out = c;
+            3'b011: out = d;
+            3'b100: out = e;
+            3'b101: out = f;
+            3'b110: out = g;
+            3'b111: out = h;
+            default: out = a;
+        endcase
+    end
+endmodule
+
+module mux_Nn1 #(
+    parameter DATA_W = 8, // bits por dato
+    parameter SEL_W = 3   // bits de sel -> 2^SEL_W entradas
+)(
+    input [(1<<SEL_W) * DATA_W - 1 : 0] in,
+    input [SEL_W-1:0] sel,
+    output [DATA_W-1:0] out
+);
+    localparam INPUTS = 1 << SEL_W; // 2^3 = 8
+
+    wire [DATA_W-1:0] data [0:INPUTS-1];
+
+    genvar i;
+    generate
+        for (i=0; i<INPUTS; i = i + 1) begin: unpack
+            assign data[i] = in[i * DATA_W +: DATA_W];
+        end
+    endgenerate
+
+    assign out = data[sel];
+endmodule

mux_demux/mux_demux_tb.v

@@ -0,0 +1,43 @@
+`include "./mux_demux/mux_demux.v"
+
+module mux_demux_tb();
+    reg [7:0] a, b;
+    reg sel;
+
+    wire [7:0] out, _a, _b;
+
+    mux_Nn1 #(.DATA_W(8), .SEL_W(1)) mux (
+        .in({b, a}),
+        .sel(sel),
+        .out(out)
+    );
+
+    demux_1n2 demux (
+        .in(out),
+        .sel(sel),
+        .a(_a),
+        .b(_b)
+    );
+
+    initial begin
+        $dumpfile("./mux_demux/mux_demux.vcd");
+        $dumpvars(0, mux_demux_tb);
+
+        a = 20; b = 5; sel = 0;
+        #1
+        $display("a=%d, b=%d, sel=%b out=%d _a=%d, _b=%d", a, b, sel, out, _a, _b);
+        a = 21; b = 5; sel = 0;
+        #1
+        $display("a=%d, b=%d, sel=%b out=%d _a=%d, _b=%d", a, b, sel, out, _a, _b);
+        a = 22; b = 5; sel = 0;
+        #1
+        $display("a=%d, b=%d, sel=%b out=%d _a=%d, _b=%d", a, b, sel, out, _a, _b);
+        a = 22; b = 5; sel = 1;
+        #1
+        $display("a=%d, b=%d, sel=%b out=%d _a=%d, _b=%d", a, b, sel, out, _a, _b);
+        a = 22; b = 15; sel = 1;
+        #1
+        $display("a=%d, b=%d, sel=%b out=%d _a=%d, _b=%d", a, b, sel, out, _a, _b);
+
+    end
+endmodule

roadmap.md

@@ -345,8 +345,8 @@ gtkwave modulo.vcd
 - [x] Fase 1.1 — Full Adder
 - [x] Fase 1.2 — Adder N bits
 - [x] Fase 1.3 — ALU basica
-- [ ] Fase 1.4 — Mux / Demux
+- [x] Fase 1.4 — Mux / Demux
-- [ ] Fase 1.5 — Decoder / Encoder
+- [x] Fase 1.5 — Decoder / Encoder
 - [ ] Fase 2.1 — Flip-Flop D y registro
 - [ ] Fase 2.2 — Contador
 - [ ] Fase 2.3 — Shift Register

run.sh

@@ -0,0 +1,16 @@
+#!/bin/bash
+
+if [ -z "$1" ]; then
+    echo "Usage: $0 <module>"
+    exit 1
+fi
+
+module="${1#./}"
+module="${module#/}"
+module="${module%/}"
+
+iverilog -o "./$module/$module.vvp" "./$module/${module}_tb.v" || exit 1
+
+vvp "./$module/$module.vvp" || exit 1
+
+surfer "./$module/$module.vcd"