update .gitignore

.gitignore

@@ -0,0 +1,3 @@
+*.vcd
+*.vvp
+*.json

counter/counter.v

@@ -0,0 +1,18 @@
+/*
+    Contador
+*/
+
+module counter #(parameter N = 8) (
+    input clk,
+    input rst,
+    input write,
+    input [N-1:0] write_value,
+    output reg [N-1:0] count
+);
+
+    always @(posedge clk or posedge rst) begin
+        if (rst) count <= 0;
+        else if (write) count <= write_value;
+        else count <= count + 1; 
+    end
+endmodule

counter/counter_tb.v

@@ -0,0 +1,44 @@
+`include "./counter/counter.v"
+
+module counter_tb;
+    reg clk, rst, write_enable;
+    reg [15:0] write_value;
+    wire [15:0] count;
+
+    counter #(.N(16)) cnt(
+        .clk(clk),
+        .rst(rst),
+        .write(write_enable),
+        .write_value(write_value),
+        .count(count)
+    );
+
+    initial clk = 0;
+    always #5 clk = ~clk;
+
+    initial begin
+        $dumpfile("./counter/counter.vcd");
+        $dumpvars(0, counter_tb);
+
+        rst = 1; write_enable = 0; write_value = 0;
+        @(posedge clk); #1
+        rst = 0;
+
+        // Contar 20 ciclos
+        repeat(20) @(posedge clk);
+        #1 $display("despues de 20 ciclos: count=%0d", count);
+
+        // Load a 200
+        write_enable = 1; write_value = 200;
+        @(posedge clk); #1
+        write_enable = 0;
+        $display("tras load 200: count=%0d", count);
+
+        // Contar hasta overflow (56 ciclos llega a 255 y desborda a 0)
+        repeat(60) @(posedge clk);
+        #1 $display("tras 60 ciclos mas: count=%0d", count);
+
+        $finish;
+    end
+
+endmodule

flip_flop/flip_flop.v

@@ -0,0 +1,17 @@
+/*
+    Flip-Flop D y registro
+*/
+
+module register #(parameter N = 8)(
+    input clk,
+    input rst,
+    input en,
+    input [N-1:0] d,
+    output reg [N-1:0] q
+);
+    always @(posedge clk or posedge rst) begin
+        if (rst) q <= 0;
+        else if (en) q <= d;
+    end
+
+endmodule

flip_flop/flip_flop_tb.v

@@ -0,0 +1,52 @@
+/*
+    Flip-Flop D y registro
+*/
+`include "./flip_flop/flip_flop.v"
+
+module register_tb;
+    reg clk, rst, en;
+    reg [7:0] d;
+    wire [7:0] q;
+
+    register #(.N(8)) dut (
+        .clk(clk),
+        .rst(rst),
+        .en(en),
+        .d(d),
+        .q(q)
+    );
+
+    initial clk = 0;
+    always #5 clk = ~clk;
+
+    initial begin
+        $dumpfile("./flip_flop/flip_flop.vcd");
+        $dumpvars(0, register_tb);
+
+        rst = 1; en = 0; d = 0;
+        @(posedge clk); #1
+
+        rst = 0;
+        @(posedge clk); #1
+        $display("rst=0, en=0, d=%0d, q=%0d (q no cambia)", d, q);
+
+        en = 1; d = 8'd42;
+        @(posedge clk); #1
+        $display("en=1, d=42 → q=%0d", q);
+
+        d = 8'd99;
+        @(posedge clk); #1
+        $display("en=1, d=99 → q=%0d", q);
+
+        en = 0; d = 8'd7;
+        @(posedge clk); #1
+        $display("en=0, d=7  → q=%0d (q mantiene 99)", q);
+
+        rst = 1;
+        @(posedge clk); #1
+        $display("rst=1      → q=%0d (q=0)", q);
+
+        $finish;
+    end
+
+endmodule

roadmap.md

@@ -347,8 +347,8 @@ gtkwave modulo.vcd
 - [x] Fase 1.3 — ALU basica
 - [x] Fase 1.4 — Mux / Demux
 - [x] Fase 1.5 — Decoder / Encoder
-- [ ] Fase 2.1 — Flip-Flop D y registro
+- [x] Fase 2.1 — Flip-Flop D y registro
-- [ ] Fase 2.2 — Contador
+- [x] Fase 2.2 — Contador
 - [ ] Fase 2.3 — Shift Register
 - [ ] Fase 2.4 — Register File
 - [ ] Fase 3.1 — RAM sincrona