`include "./counter/counter.v"

module counter_tb;
    reg clk, rst, write_enable;
    reg [15:0] write_value;
    wire [15:0] count;

    counter #(.N(16)) cnt(
        .clk(clk),
        .rst(rst),
        .write(write_enable),
        .write_value(write_value),
        .count(count)
    );

    initial clk = 0;
    always #5 clk = ~clk;

    initial begin
        $dumpfile("./counter/counter.vcd");
        $dumpvars(0, counter_tb);

        rst = 1; write_enable = 0; write_value = 0;
        @(posedge clk); #1
        rst = 0;

        // Contar 20 ciclos
        repeat(20) @(posedge clk);
        #1 $display("despues de 20 ciclos: count=%0d", count);

        // Load a 200
        write_enable = 1; write_value = 200;
        @(posedge clk); #1
        write_enable = 0;
        $display("tras load 200: count=%0d", count);

        // Contar hasta overflow (56 ciclos llega a 255 y desborda a 0)
        repeat(60) @(posedge clk);
        #1 $display("tras 60 ciclos mas: count=%0d", count);

        $finish;
    end

endmodule