/*
    ROM
*/
`include "rom/rom.v"

module rom_tb;
    reg clk;
    reg [7:0]   addr;
    wire [15:0] rd_data;

    rom #(.FILE("rom/program.hex")) rom1(
        .clk(clk),
        .addr(addr),
        .rd_data(rd_data)
    );

    initial clk = 0;
    always #5 clk = ~clk;

    initial begin
        $dumpfile("rom/rom.vcd");
        $dumpvars(0, rom_tb);

        addr = 0;
        @(posedge clk);
        $display("addr=%d, rd_data=%x", addr, rd_data);
        @(posedge clk);
        $display("addr=%d, rd_data=%x", addr, rd_data);

        addr = 1;
        @(posedge clk);
        $display("addr=%d, rd_data=%x", addr, rd_data);
        @(posedge clk);
        $display("addr=%d, rd_data=%x", addr, rd_data);

        addr = 2;
        @(posedge clk);
        $display("addr=%d, rd_data=%x", addr, rd_data);
        @(posedge clk);
        $display("addr=%d, rd_data=%x", addr, rd_data);
        
        $finish;
    end
endmodule