/*
    Flip-Flop D y registro
*/
`include "./flip_flop/flip_flop.v"

module register_tb;
    reg clk, rst, en;
    reg [7:0] d;
    wire [7:0] q;

    register #(.N(8)) dut (
        .clk(clk),
        .rst(rst),
        .en(en),
        .d(d),
        .q(q)
    );

    initial clk = 0;
    always #5 clk = ~clk;

    initial begin
        $dumpfile("./flip_flop/flip_flop.vcd");
        $dumpvars(0, register_tb);

        rst = 1; en = 0; d = 0;
        @(posedge clk); #1

        rst = 0;
        @(posedge clk); #1
        $display("rst=0, en=0, d=%0d, q=%0d (q no cambia)", d, q);

        en = 1; d = 8'd42;
        @(posedge clk); #1
        $display("en=1, d=42 → q=%0d", q);

        d = 8'd99;
        @(posedge clk); #1
        $display("en=1, d=99 → q=%0d", q);

        en = 0; d = 8'd7;
        @(posedge clk); #1
        $display("en=0, d=7  → q=%0d (q mantiene 99)", q);

        rst = 1;
        @(posedge clk); #1
        $display("rst=1      → q=%0d (q=0)", q);

        $finish;
    end

endmodule