/*
    Stack testbench
*/

`include "stack/stack.v"

module stack_tb;
    reg clk, rst, push, pop;
    reg[15:0]   in;
    wire [15:0] out;

    stack stack1(
        .clk(clk),
        .rst(rst),
        .push(push),
        .pop(pop),
        .value(in),
        .out(out)
    );

    initial clk = 0;
    always #5 clk = ~clk;

    initial begin
        $dumpfile("stack/stack.vcd");
        $dumpvars(0, stack_tb);

        rst = 1; push = 0; pop = 0; in = 0;
        @(posedge clk); #1
        rst = 0;
        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);

        push = 1; pop = 0; in = 69;
        @(posedge clk); #1
        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);

        push = 1; pop = 0; in = 40;
        @(posedge clk); #1
        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);

        push = 0; pop = 0; in = 0;
        @(posedge clk); #1
        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);

        push = 0; pop = 1; in = 0;
        @(posedge clk); #1
        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
        push = 0; pop = 0; in = 0;
        @(posedge clk); #1
        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);


        push = 0; pop = 1; in = 0;
        @(posedge clk); #1 
        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
        push = 0; pop = 0; in = 0;
        @(posedge clk); #1
        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);


        $finish;
    end
endmodule