`include "./shift_register/shift_register.v"

module shift_register_tb;
    reg clk, rst, load, shift_en, dir, serial_in;
    reg [7:0] parallel_in;
    wire [7:0] q;
    wire serial_out;

    shift_register register(
        .clk(clk),
        .rst(rst),
        .load(load),
        .shift_en(shift_en),
        .dir(dir),
        .serial_in(serial_in),
        .parallel_in(parallel_in),
        .q(q),
        .serial_out(serial_out)
    );

    initial clk = 0;
    always #5 clk = ~clk;

    initial begin
        $dumpfile("./shift_register/shift_register.vcd");
        $dumpvars(0, shift_register_tb);

        rst = 1; load = 0; shift_en = 1; dir = 0; serial_in = 0;
        @(posedge clk);

        $display("rst=%b, load=%b, shift_en=%b, dir=%b, serial_in=%b, q=%b", rst, load, shift_en, dir, serial_in, q);

        rst = 0; load = 1; parallel_in = 64;
        @(posedge clk);

        $display("rst=%b, load=%b, shift_en=%b, dir=%b, serial_in=%b, q=%b", rst, load, shift_en, dir, serial_in, q);

        load = 0; serial_in = 1;
        @(posedge clk);
        $display("rst=%b, load=%b, shift_en=%b, dir=%b, serial_in=%b, q=%b", rst, load, shift_en, dir, serial_in, q);

        repeat(10) @(posedge clk);
        $display("rst=%b, load=%b, shift_en=%b, dir=%b, serial_in=%b, q=%b", rst, load, shift_en, dir, serial_in, q);

        $finish;
    end

endmodule