/*
    Registros
*/

module register_file #(
    parameter REGS = 16,
    parameter W    = 16
) (
    input                       clk,
    input                       rst,
    // Puerto escritura
    input [$clog2(REGS)-1:0]    wr_addr,
    input [W-1:0]               wr_data,
    input                       wr_en,
    // Puerto lectura 1
    input [$clog2(REGS)-1:0]    rd_addr1,
    output [W-1:0]              rd_data1,
    // Puerto lectura 2
    input [$clog2(REGS)-1:0]    rd_addr2,
    output [W-1:0]              rd_data2
);
    reg [W-1:0] regs [0:REGS-1];

    // Lectura combinacional
    assign rd_data1 = regs[rd_addr1];
    assign rd_data2 = regs[rd_addr2];

    // Escritura sincrona
    integer i;
    always @(posedge clk or posedge rst) begin
       if (rst) begin
        for (i = 0; i < REGS; i = i + 1)
            regs[i] <= 0;
       end else if (wr_en) begin
            regs[wr_addr] <= wr_data;
       end
    end
endmodule