`include "./adder_nbit/adder_nbit.v"

module adder_nbit_tb;
    reg [7:0] a, b;
    reg carry_in;

    wire [7:0] sum;
    wire carry_out;

    adder_nbit adder_8bit(
        .a(a),
        .b(b),
        .carry_in(carry_in),
        .sum(sum),
        .carry_out(carry_out)
    );

    initial begin
        $dumpfile("./adder_nbit/adder_nbit.vcd");
        $dumpvars(0, adder_nbit_tb);

        a = 0; b = 5; carry_in = 0;
        #1
        $display("a=%d, b=%d, sum=%d, carry=%b", a, b, sum, carry_out);
        a = 10; b = 5; carry_in = 0;
        #1
        $display("a=%d, b=%d, sum=%d, carry=%b", a, b, sum, carry_out);
        a = 100; b = 5; carry_in = 0;
        #1
        $display("a=%d, b=%d, sum=%d, carry=%b", a, b, sum, carry_out);

    end 

endmodule