/*
    Half Adder Declaration
*/

module half_adder (a,b,sum,carry);
    input a,b;
    output sum, carry;

    xor x1(sum, a, b);
    and a1(carry, a, b);
endmodule

module half_adder_dataflow (a, b, sum, carry);
    input a, b;
    output sum, carry;

    assign sum = a ^ b;
    assign carry = a & b;
endmodule

module half_adder_behavioral (a, b, sum, carry);
    input a, b;
    output reg sum, carry;

    always @(a or b) begin
        sum = a ^ b;
        carry = a & b;
    end
endmodule