/*
    Registros
*/
`include "./register_file/register_file.v"
module register_file_tb;
    reg clk, rst, wr_en;
    reg [3:0] wr_addr;
    reg [15:0] wr_data;
    reg [3:0] rd_addr1, rd_addr2;
    wire [15:0] rd_value1, rd_value2;

    register_file register(
        .clk(clk),
        .rst(rst),
        .wr_addr(wr_addr),
        .wr_data(wr_data),
        .wr_en(wr_en),
        .rd_addr1(rd_addr1),
        .rd_data1(rd_value1),
        .rd_addr2(rd_addr2),
        .rd_data2(rd_value2)
    );

    initial clk = 0;
    always #5 clk = ~clk;

    initial begin
        $dumpfile("register_file/register_file.vcd");
        $dumpvars(0, register_file_tb);

        rst = 1; wr_en = 0; wr_addr = 0; wr_data = 0;
        rd_addr1 = 0; rd_addr2 = 0;
        @(posedge clk);
        $display("rst=%b, wr_en=%b, wr_add=%d, wr_data=%d", rst, wr_en, wr_addr, wr_data);
        $display("rd_addr1=%d, rd_addr2=%d, rd_value1=%d, rd_value2=%d", rd_addr1, rd_addr2, rd_value1, rd_value2);

        rst = 0;
        @(posedge clk);
        $display("rst=%b, wr_en=%b, wr_add=%d, wr_data=%d", rst, wr_en, wr_addr, wr_data);
        $display("rd_addr1=%d, rd_addr2=%d, rd_value1=%d, rd_value2=%d", rd_addr1, rd_addr2, rd_value1, rd_value2);

        wr_en = 1; wr_addr = 1; wr_data = 16'hBEEF;
        @(posedge clk);
        $display("rst=%b, wr_en=%b, wr_add=%d, wr_data=%d", rst, wr_en, wr_addr, wr_data);
        $display("rd_addr1=%d, rd_addr2=%d, rd_value1=%d, rd_value2=%d", rd_addr1, rd_addr2, rd_value1, rd_value2);

        wr_en = 0;
        @(posedge clk);
        $display("rst=%b, wr_en=%b, wr_add=%d, wr_data=%d", rst, wr_en, wr_addr, wr_data);
        $display("rd_addr1=%d, rd_addr2=%d, rd_value1=%d, rd_value2=%d", rd_addr1, rd_addr2, rd_value1, rd_value2);

        rd_addr1 = 1;
        @(posedge clk);
        $display("rst=%b, wr_en=%b, wr_add=%d, wr_data=%d", rst, wr_en, wr_addr, wr_data);
        $display("rd_addr1=%d, rd_addr2=%d, rd_value1=%d, rd_value2=%d", rd_addr1, rd_addr2, rd_value1, rd_value2);

        repeat(100) @(posedge clk);
        $finish;
    end
endmodule