57 lines
1.1 KiB
Verilog
57 lines
1.1 KiB
Verilog
/*
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fsm_traffic testbench
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*/
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`include "fsm_traffic/fsm_traffic.v"
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module fsm_traffic_tb;
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reg clk, rst;
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wire red_led, green_led, yellow_led;
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fsm_traffic dut (
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.clk(clk),
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.rst(rst),
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.red_led(red_led),
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.green_led(green_led),
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.yellow_led(yellow_led)
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);
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initial clk = 0;
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always #5 clk = ~clk;
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task show_state;
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$display("t=%0t | rst=%b | R=%b G=%b Y=%b",
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$time, rst, red_led, green_led, yellow_led);
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endtask
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initial begin
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$dumpfile("fsm_traffic/fsm_traffic.vcd");
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$dumpvars(0, fsm_traffic_tb);
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// Reset
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rst = 1;
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@(posedge clk); #1
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show_state;
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rst = 0;
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// Dejar correr varios ciclos para ver todos los estados
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repeat(9) begin
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@(posedge clk); #1
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show_state;
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end
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// Reset a mitad de secuencia — debe volver a RED
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rst = 1;
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@(posedge clk); #1
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show_state;
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rst = 0;
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repeat(3) begin
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@(posedge clk); #1
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show_state;
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end
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$finish;
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end
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endmodule
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