18 lines
340 B
Verilog
18 lines
340 B
Verilog
/*
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Contador
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*/
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module counter #(parameter N = 8) (
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input clk,
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input rst,
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input write,
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input [N-1:0] write_value,
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output reg [N-1:0] count
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);
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always @(posedge clk or posedge rst) begin
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if (rst) count <= 0;
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else if (write) count <= write_value;
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else count <= count + 1;
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end
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endmodule |