45 lines
1.1 KiB
Verilog
45 lines
1.1 KiB
Verilog
/*
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Full Adder Declaration
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A B Cin | Sum Cout
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0 0 0 | 0 0
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0 0 1 | 1 0
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0 1 0 | 1 0
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0 1 1 | 0 1
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1 0 0 | 1 0
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1 0 1 | 0 1
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1 1 0 | 0 1
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1 1 1 | 1 1
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*/
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`include "./half_adder/half_adder.v"
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module full_adder_structural (carry_in, a, b, sum, carry_out);
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input carry_in, a, b;
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output sum, carry_out;
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wire add1_sum, add1_carry;
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wire add2_carry;
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half_adder add1(a, b, add1_sum, add1_carry);
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half_adder add2(add1_sum, carry_in, sum, add2_carry);
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or final_or(carry_out, add1_carry, add2_carry);
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endmodule
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module full_adder_dataflow (carry_in, a, b, sum, carry_out);
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input carry_in, a, b;
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output sum, carry_out;
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assign sum = a ^ b ^ carry_in;
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assign carry_out = (a & b) | (carry_in & (a ^ b));
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endmodule
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module full_adder_behavioral (carry_in, a, b, sum, carry_out);
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input carry_in, a, b;
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output reg sum, carry_out;
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always @(*) begin
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sum = a ^ b ^ carry_in;
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carry_out = (a & b) | (carry_in & (a ^ b));
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end
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endmodule |