admin/hdl-projects
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
6df702470720313c13a5b860d6e5fc27f7820180
hdl-projects/half_adder/readme.md
Jose Luis Montañes Ojados d094ff3148 first commit
2026-02-28 21:59:55 +01:00

195 B
Raw Blame History

  1. Compilar el testbench iverilog -o .\half_adder_tb.vvp .\half_adder_tb.v

  2. Ejecutar simulacion del testbench vvp .\half_adder_tb.vvp

  3. Visualizar ondas gtkwave .\half_adder.vcd

Reference in New Issue View Git Blame Copy Permalink