34 lines
527 B
Verilog
34 lines
527 B
Verilog
/*
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Mux / Demux
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Mux
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a b sel | out
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-------------------
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0 0 0 | 0
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1 0 0 | 1
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0 1 1 | 1
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1 0 1 | 0
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...
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*/
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module mux_2n1 #(parameter N = 8) (
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input [N-1:0] a,
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input [N-1:0] b,
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input sel,
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output [N-1:0] out
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);
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assign out = sel ? b : a;
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endmodule
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module demux_1n2 #(parameter N = 8) (
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input [N-1:0] in,
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input sel,
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output [N-1:0] a,
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output [N-1:0] b
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);
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assign a = sel ? 0 : in;
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assign b = sel ? in : 0;
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endmodule |