44 lines
1.0 KiB
Verilog
44 lines
1.0 KiB
Verilog
`include "./counter/counter.v"
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module counter_tb;
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reg clk, rst, write_enable;
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reg [15:0] write_value;
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wire [15:0] count;
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counter #(.N(16)) cnt(
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.clk(clk),
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.rst(rst),
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.write(write_enable),
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.write_value(write_value),
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.count(count)
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);
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initial clk = 0;
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always #5 clk = ~clk;
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initial begin
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$dumpfile("./counter/counter.vcd");
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$dumpvars(0, counter_tb);
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rst = 1; write_enable = 0; write_value = 0;
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@(posedge clk); #1
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rst = 0;
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// Contar 20 ciclos
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repeat(20) @(posedge clk);
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#1 $display("despues de 20 ciclos: count=%0d", count);
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// Load a 200
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write_enable = 1; write_value = 200;
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@(posedge clk); #1
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write_enable = 0;
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$display("tras load 200: count=%0d", count);
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// Contar hasta overflow (56 ciclos llega a 255 y desborda a 0)
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repeat(60) @(posedge clk);
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#1 $display("tras 60 ciclos mas: count=%0d", count);
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$finish;
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end
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endmodule |