38 lines
871 B
Verilog
38 lines
871 B
Verilog
`include "./decoder_encoder/decoder_encoder.v"
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module decoder_3bit_tb;
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reg [2:0] in;
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wire [7:0] out;
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wire [2:0] encoded;
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decoder_3bit dec(
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.in(in),
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.out(out)
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);
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encoder_3bit enc(
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.in(out),
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.out(encoded)
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);
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initial begin
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$dumpfile("./decoder_encoder/decoder_encoder.vcd");
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$dumpvars(0, decoder_3bit_tb);
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in = 3'b000;
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#1
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$display("in=%d, out=%b, enc=%d", in, out, encoded);
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in = 3'b001;
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#1
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$display("in=%d, out=%b, enc=%d", in, out, encoded);
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in = 3'b010;
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#1
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$display("in=%d, out=%b, enc=%d", in, out, encoded);
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in = 3'b100;
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#1
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$display("in=%d, out=%b, enc=%d", in, out, encoded);
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in = 3'b111;
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#1
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$display("in=%d, out=%b, enc=%d", in, out, encoded);
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end
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endmodule |