26 lines
456 B
Verilog
26 lines
456 B
Verilog
/*
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Testbench for half_adder
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*/
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`include "./half_adder/half_adder.v"
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module half_adder_tb;
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reg a, b;
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wire sum, carry;
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half_adder add1(a, b, sum, carry);
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initial begin
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$dumpfile("./half_adder/half_adder.vcd");
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$dumpvars(0, half_adder_tb);
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a = 0; b = 0;
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#1
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a = 0; b = 1;
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#1
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a = 1; b = 0;
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#1
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a = 1; b = 1;
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#1
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a = 0; b = 0;
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end
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endmodule |