33 lines
748 B
Verilog
33 lines
748 B
Verilog
/*
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Stack
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*/
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module stack #(
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parameter DEPTH = 256,
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parameter W = 16
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) (
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input clk,
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input rst,
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input push,
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input pop,
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input [W-1:0] value,
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output reg [W-1:0] out
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);
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reg [W-1:0] mem [0:DEPTH-1];
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reg [$clog2(DEPTH):0] sp; // bit extra para detectar overflow
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wire full = (sp == DEPTH);
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wire empty = (sp == 0);
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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sp <= 0;
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end else if (push && !full) begin
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mem[sp] <= value;
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sp <= sp + 1;
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end else if (pop && !empty) begin
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out <= mem[sp - 1];
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sp <= sp - 1;
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end
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end
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endmodule |