# Especificaciones Arquitectura: 16bit Tamaño de instruccion: 16bit PROM: Ilimitado RAM: 1kB - 20kB STACK: 256 - Ilimitado # Registros Cada registro puede almacenar 16 bits | ADDR | NAME | NOTES | | ---- | -------- | --------- | | 0x00 | REG0 | | | 0x01 | REG1 | | | 0x02 | REG2 | | | 0x03 | REG3 | | | 0x04 | REG4 | | | 0x05 | REG5 | | | 0x06 | REG6 | | | 0x07 | REG7 | | | 0x08 | REG8 | | | 0x09 | REG9 | | | 0x0A | REG10 | | | 0x0B | REG11 | | | 0x0C | REG12 | RAM VALUE | | 0x0D | REG13 | RAM ADDR | | 0x0E | PC | | | 0x0F | IN/OUT | | # Opcodes Las instrucciones en este CPU tienen un tamaño total de 8 bytes, es decir, 4 parametros de 16bit cada uno. [OPCODE] [PARAM1] [PARAM2] [TARGET1] PARAM1 y PARAM2 soportan 2 modos de direccionamiento: - Modo registro - Modo inmediato TARGET1 indica el registro donde se guardará el resultado. ## ALU | OPCODE | ADDR | PARAM1 | PARAM2 | TARGET1 | DESCRIPTION | | ------ | ---- | ------ | ------ | ------- | ----------- | | ADD | 0x00 | R0 | R1 | T1 | | | SUB | 0x01 | R0 | R1 | T1 | | | MUL | 0x02 | R0 | R1 | T1 | | | DIV | 0x03 | R0 | R1 | T1 | | | AND | 0x04 | R0 | R1 | T1 | | | OR | 0x05 | R0 | R1 | T1 | | | NOT | 0x06 | R0 | R1 | T1 | | | NAND | 0x07 | R0 | R1 | T1 | | | NOR | 0x08 | R0 | R1 | T1 | | | XOR | 0x09 | R0 | R1 | T1 | | | XNOR | 0x0A | R0 | R1 | T1 | | | NEG | 0x0B | R0 | R1 | T1 | | | - | 0x0C | | | | | | - | 0x0D | | | | | | - | 0x0E | | | | | | - | 0x0F | | | | | | ------ | ---- | ------ | ------ | ------- | ----------- | | ADD | 0x40 | #0 | R1 | T1 | | | SUB | 0x41 | #0 | R1 | T1 | | | MUL | 0x42 | #0 | R1 | T1 | | | DIV | 0x43 | #0 | R1 | T1 | | | AND | 0x44 | #0 | R1 | T1 | | | OR | 0x45 | #0 | R1 | T1 | | | NOT | 0x46 | #0 | R1 | T1 | | | NAND | 0x47 | #0 | R1 | T1 | | | NOR | 0x48 | #0 | R1 | T1 | | | XOR | 0x49 | #0 | R1 | T1 | | | XNOR | 0x4A | #0 | R1 | T1 | | | NEG | 0x4B | #0 | R1 | T1 | | | - | 0x4C | | | | | | - | 0x4D | | | | | | - | 0x4E | | | | | | - | 0x4F | | | | | | ------ | ---- | ------ | ------ | ------- | ----------- | | ADD | 0x80 | R0 | #1 | T1 | | | SUB | 0x81 | R0 | #1 | T1 | | | MUL | 0x82 | R0 | #1 | T1 | | | DIV | 0x83 | R0 | #1 | T1 | | | AND | 0x84 | R0 | #1 | T1 | | | OR | 0x85 | R0 | #1 | T1 | | | NOT | 0x86 | R0 | #1 | T1 | | | NAND | 0x87 | R0 | #1 | T1 | | | NOR | 0x88 | R0 | #1 | T1 | | | XOR | 0x89 | R0 | #1 | T1 | | | XNOR | 0x8A | R0 | #1 | T1 | | | NEG | 0x8B | R0 | #1 | T1 | | | - | 0x8C | | | | | | - | 0x8D | | | | | | - | 0x8E | | | | | | - | 0x8F | | | | | | ------ | ---- | ------ | ------ | ------- | ----------- | | ADD | 0xC0 | #0 | #1 | T1 | | | SUB | 0xC1 | #0 | #1 | T1 | | | MUL | 0xC2 | #0 | #1 | T1 | | | DIV | 0xC3 | #0 | #1 | T1 | | | AND | 0xC4 | #0 | #1 | T1 | | | OR | 0xC5 | #0 | #1 | T1 | | | NOT | 0xC6 | #0 | #1 | T1 | | | NAND | 0xC7 | #0 | #1 | T1 | | | NOR | 0xC8 | #0 | #1 | T1 | | | XOR | 0xC9 | #0 | #1 | T1 | | | XNOR | 0xCA | #0 | #1 | T1 | | | NEG | 0xCB | #0 | #1 | T1 | | | - | 0xCC | | | | | | - | 0xCD | | | | | | - | 0xCE | | | | | | - | 0xCF | | | | | ## CONDITIONALS En los condicionales TARGET1 representa a la direccion del PC (Program Counter) que se saltará si se cumple la condicion. | OPCODE | ADDR | PARAM1 | PARAM2 | TARGET1 | DESCRIPTION | | ------ | ---- | ------ | ------ | ------- | ----------- | | EQ | 0x10 | R0 | R1 | T1 | equal | | NEQ | 0x11 | R0 | R1 | T1 | not equal | | LS | 0x12 | R0 | R1 | T1 | less | | LSE | 0x13 | R0 | R1 | T1 | less or eq | | GR | 0x14 | R0 | R1 | T1 | greater | | GRE | 0x15 | R0 | R1 | T1 |greater or eq| | | 0x16 | R0 | R1 | T1 | | | | 0x17 | R0 | R1 | T1 | | | ------ | ---- | ------ | ------ | ------- | ----------- | | EQ | 0x50 | #0 | R1 | T1 | equal | | NEQ | 0x51 | #0 | R1 | T1 | not equal | | LS | 0x52 | #0 | R1 | T1 | less | | LSE | 0x53 | #0 | R1 | T1 | less or eq | | GR | 0x54 | #0 | R1 | T1 | greater | | GRE | 0x55 | #0 | R1 | T1 |greater or eq| | | 0x56 | #0 | R1 | T1 | | | | 0x57 | #0 | R1 | T1 | | | ------ | ---- | ------ | ------ | ------- | ----------- | | EQ | 0x90 | R0 | #1 | T1 | equal | | NEQ | 0x91 | R0 | #1 | T1 | not equal | | LS | 0x92 | R0 | #1 | T1 | less | | LSE | 0x93 | R0 | #1 | T1 | less or eq | | GR | 0x94 | R0 | #1 | T1 | greater | | GRE | 0x95 | R0 | #1 | T1 |greater or eq| | | 0x96 | R0 | #1 | T1 | | | | 0x97 | R0 | #1 | T1 | | | ------ | ---- | ------ | ------ | ------- | ----------- | | EQ | 0xD0 | #0 | #1 | T1 | equal | | NEQ | 0xD1 | #0 | #1 | T1 | not equal | | LS | 0xD2 | #0 | #1 | T1 | less | | LSE | 0xD3 | #0 | #1 | T1 | less or eq | | GR | 0xD4 | #0 | #1 | T1 | greater | | GRE | 0xD5 | #0 | #1 | T1 |greater or eq| | | 0xD6 | #0 | #1 | T1 | | | | 0xD7 | #0 | #1 | T1 | | ## CONTROL UNIT | OPCODE | ADDR | PARAM1 | PARAM2 | TARGET1 | DESCRIPTION | | ------ | ---- | ------ | ------ | ------- | ----------- | | RSTR | 0x18 | -- | -- | - | | | PUSH | 0x19 | R1 | -- | - | | | POP | 0x1A | -- | -- | T1 | | | ------ | ---- | ------ | ------ | ------- | ----------- | | PUSH | 0x59 | #1 | -- | - | | ## FUNCTIONS | OPCODE | ADDR | PARAM1 | PARAM2 | TARGET1 | DESCRIPTION | | ------ | ---- | ------ | ------ | ------- | ----------- | | CALL | 0x20 | R1 | -- | - | | | RET | 0x21 | -- | -- | - | | | HALT | 0x22 | -- | -- | - | | | ------ | ---- | ------ | ------ | ------- | ----------- | | CALL | 0x60 | #1 | -- | - | |